A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS

Abstract

This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback equalizer (DFE) fabricated in 28-nm CMOS. The proposed on-chip adaptation engine is tailored to a baud-rate CDR, where the front-end comparators are shared between the DFE and the PD to save power. The adaptive scheme is demonstrated on a baud-rate CDR testchip that has sampler-based front-end equalization which is more suitable for low-power, short reach, applications instead of a power intensive ADC/DSP-based receiver approach that is usually meant for long-reach (LR) links. This testchip was validated with 34–36 Gb/s random input data (PRBS31 & 7) with channel loss of 15.05–18.25 dB at Nyquist. The total power consumption is measured to be 106.3 mW, equivalent to an FOM of 3.04 pJ/bit at 35 Gb/s.