A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller

Abstract

To improve the jitter tolerance (JTOL) of a clock and data recovery (CDR) circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of $2^{15}$ -1 and the bit error rate $ , the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UIpp.