A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit

Abstract

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5[Formula: see text]Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector’s phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit’s total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40[Formula: see text]nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5[Formula: see text]Gb/s. With a pseudo-random bit sequence (PRBS) of [Formula: see text], the measured result shows that the bit error rate (BER) is [Formula: see text], and the root mean square jitter recovered in the output is 0.302 [Formula: see text]. The circuit’s jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8[Formula: see text]mW with a 5.98[Formula: see text]pJ/bit energy efficiency.