Wafer Cleaning Research Articles

Low-Temperature Electrical Performance of PureB Photodiodes Revealing Al-Metallization-Related Degradation of Dark Currents

Pure boron (PureB) deposition as the anode region of Si photodiodes creates negative fixed charge at the boron/silicon interface, which is responsible for effective suppression of electron injection from the bulk, thus ensuring low saturation/dark current densities. This mechanism is shown here to remain effective when PureB diodes, fabricated at 700 °C, are operated at cryogenic temperatures down to 100 K. Although the PureB junctions were only a few nanometers deep, they displayed the same current-voltage ( I- V) characteristics as conventional deep diffused p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -n junction diodes in the whole temperature range and also maintained ideality factors close to n = 1. Al-contacting was found to reveal process-related defects in the form of anomalous high current regions giving kinks in the I- V characteristics, often only visible at low temperatures. They were identified as minute Al-Si Schottky junctions with an effective barrier height of ~0.65 ± 0.05 eV. In PureB single-photon avalanche diodes (SPADs), Al-Si perimeter defects appeared but did not affect the breakdown voltage characteristics set by implicit guard rings. Low series resistance required thin B-layers that promoted tunneling. In particular, for such thin layers, avoiding Al-related degradation puts stringent requirements on wafer cleaning and window etch procedures.

Analysis of Wafer Cleaning Solution Characteristics and Metal Dissolution Behavior according to the Addition of Chelating Agent

Analysis of Wafer Cleaning Solution Characteristics and Metal Dissolution Behavior according to the Addition of Chelating Agent

High Performance, Eco-Friendly SPM Cleaning Technology Using Integrated Bench-Single Wafer Cleaning System

Batch SPM systems do not meet the current clean specification/requirements below 28nm. Single wafer SPM systems use a high volume of chemistry which runs to drain, while meeting the cleaning specifications below 28nm. The work in this paper describe the use of a batch SPM system and a single wafer clean in an integrated system, Ultra-C Tahoe which results in meeting the technical specification and using less that 80% of the SPM chemistry used in single wafer systems. The data collected shows this new system meet the specifications, whilst saving more than 80%of SPM chemistry.

Tribological Characterization of Anionic Supramolecular Assemblies in Post-STI-CMP Cleaning Solution Using a Novel Post-CMP PVA Brush Scrubber

We have shown how different micellar (SDBS) vs. polyelectrolytic (PSSA) supramolecular assemblies in post-CMP cleaning solutions differ in their tribological performance when used in a novel PVA scrubber for 300-mm silicon dioxide wafer cleaning. Significant differences in real-time shear force and coefficient of friction data from the wafer-solution-brush interface (both in time domain as well as frequency domain) have been attributed to differences in each supramolecule’s chemical functionality and structure, which in turn, have been correlated to wafer-level defects. The work has underscored the importance of measuring the tribological attributes of post-CMP cleaning processes in an effort to improve cleaning performance.

Dissolution Behavior of Metal Impurities and Improvement of Reclaimed Semiconductor Wafer Cleaning by Addition of Chelating Agent

Dissolution Behavior of Metal Impurities and Improvement of Reclaimed Semiconductor Wafer Cleaning by Addition of Chelating Agent

Dripping–jetting transition of liquid stream from plate-type micro-orifice affected by wetting and dewetting

The liquid stream from an orifice typically undergoes a transition process from dripping to jetting under increased pressure. The dripping–jetting (D–J) transition performance from a thin-walled tube or an orifice with a wide diameter has been well studied, where the triple contact line of the stream is pinned on the edge of the orifice and the flow behaviors are analyzed accordingly with a precondition of the fixed contact line. The D–J transition of the liquid stream from plate-type micro-orifices was investigated in our study of droplet generation for extreme ultraviolet source and wafer cleaning. The triple contact line of the stream keeps moving as pressure changes as a result of the liquid wetting and dewetting around the micro-orifice. The transition from dripping to jetting involves three processes: wetting to generate pendant droplet and dripping, jetting from pendant droplet, and pendant droplet dewetting to form jetting directly. The aforementioned performance is different from boundary-pinned conditions. To reveal the transition characteristic, critical pressure causing the D–J transition under different wetting conditions was determined. The process of wetting to generate pendant droplet and dripping, and the effects of the contact angle and the pressure difference were formulated. Analysis of the mechanism causing jetting from the pendant droplet was implemented by combining a model formulating the jet ejecting outside the droplet and numerical simulation of the stream inside the pendant droplet. Finally, the normalized model was built to illustrate the critical pressure of D–J transition concerning the triple contact line diameter.

Optimal Design of High-Frequency Induction Heating Apparatus for Wafer Cleaning Equipment Using Superheated Steam

In this study, wafer cleaning equipment was designed and fabricated using the induction heating (IH) method and a short-time superheated steam (SHS) generation process. To prevent problems arising from the presence of particulate matter in the fluid flow region, pure grade 2 titanium (Ti) R50400 was used in the wafer cleaning equipment for heating objects via induction. The Ti load was designed and manufactured with a specific shape, along with the resonant network, to efficiently generate high-temperature steam by increasing the residence time of the fluid in the heating object. The IH performance of various shapes of heating objects made of Ti was analyzed and the results were compared. In addition, the heat capacity required to generate SHS was mathematically calculated and analyzed. The SHS heating performance was verified by conducting experiments using the designed 2.2 kW wafer cleaning equipment. The performance of the proposed pure Ti-based SHS generation system was found to be satisfactory, and SHS with a temperature higher than 200 °C was generated within 10 s using this system.

Study on Influence of O2 Concentration in Wafer Cleaning Ambient for Smoothness of Silicon (110) Surface Appearing at Sidewall of Three-Dimensional Transistors

The Si(110) surface appears at the sidewall of 3D transistors such as FinFET [1,2]. The surface micro-roughness of Si(110) strongly affects to the device characteristics because the Si(110) sidewall surface have a higher proportion of channel region width the miniaturization of width of fin structure [1,2]. In this work, we investigated the ambient in the wafer cleaning process to keep the smoothness of Si(110) surface.The wafers used in this study were Cz p-type Si(110) substrates having nearly 10 Ωcm. The wet oxidation of these substrates was performed at 1000 °C to form 300nm-thick silicon oxide films. Just after this oxide films were removed by HF solution, the average surface microroughness (Ra) of Si(110) measured by atomic force microscopy (AFM) was about 0.073 nm. We evaluated the influence of O2 concentration during the immersion in ultra pure water (UPW) by using N2 sealed glove box. The N2 sealed glove box can be controlled O2 concentration from 20% to 30 ppm. After the removing the chemical oxide with a diluted HF (0.5wt %) solution in this glove box with O2 concentration of 100 ppm, the wafers were immersed in UPW. We also evaluated for SOI wafer (20nm-thick Si(110) layer / 400nm-thick BOX layer / 725μm-thick Si(110) substrate) in a similar way.Figure 1 shows AFM images of Si(110) surface (a) before and after immersion in UPW for 24 hour in (b) 20% O2 (atmosphere) and (c) N2 ambient with O2 concertation less than 100ppm by using glove box. Ra drastically increase in the case of 20% O2 concentration. On the other hand, the increase of Ra is suppressed in N2 ambient with O2 concertation less than 100ppm. This indicates that the controlling of O2 concertation of ambient during the immersion in UPW is very effective to suppress the increase of Ra of Si(110) surface. It has been reported that the increase of Ra is caused by Si dissolving in UPW and Si dissolving in UPW is caused by the local oxidation just on Si surface [3,4].Figure 2 shows AFM images of Si(110) surface after immersion in UPW for 1, 3 and 24 hour in N2 ambient with O2 concertation of 100ppm. During the immersion in UPW, the O2 concentration was held 100 ppm. Figure 3 shows Ra as a function of immersion time for Si(110) surface in N2 ambient with O2 concertation of 100ppm. As increasing immersion time, the Ra is increasing. In addition, the line-formed roughness to <110> direction and the local bumps are appeared on the Si(110) surface. However, the Ra of immersion for 1 hour is not almost change from the initial Ra. Moreover, Si atoms eluted in UPW for 24 hours calculated from the decrease of SOI thickness was less than 4.0×1014/cm2 per 1hour. This means that the amount of elution of Si atoms in UPW within 1 hour is less than 1 atomic layer because the areal density of Si(110) orientation substrate is 9.6×1014/cm2 [5]. In the actual wafer cleaning process, the time of UPW attaching to wafer surface is far shorter than 1 hour. Therefore, when the O2 concentration is controlled less than 100ppm in the wafer cleaning process, it can be expected that Si(110) surface of sidewall of 3D transistor is not roughened and the shape of Si fin structure is kept. Furthermore, we evaluate the O2 concentration by using the prototype 200mm single wafer cleaning chamber. We demonstrated that the O2 concentration in this chamber can be decreased less than 100ppm within 1 minute by N2 purge of 200 L/min.AcknowledgementsThis work is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO) and was carried out at the Fluctuation Free Facility (FFF) of New Industry Creation Hatchery Center, Tohoku University.Reference[1] D. James, 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 324-329, May 2016.[2] A. Teramoto et al., IEEE Trans. Electron Devices, vol 54, No 6, pp. 1438-1443, 2007.[3] H. Morinaga, et al., Solid State Phenomena, Vol.134, pp.45-48, 2007.[4] K. Nii, et al., 206th Meeting of The Electrochemical Society, 2004.[5] M. Higuchi, et al., Appl. Phys. Lett. 90 Number 12, pp. 123114-1-123114-3, 2007. Figure 1

Study on Influence of O2 Concentration in Wafer Cleaning Ambient for Smoothness of Silicon (110) Surface Appearing at Sidewall of Three-Dimensional Transistors

We investigated the influence of O2 concentration in ultra pure water (UPW) on the Si(110) surface roughness during the immersion of Si into UPW. The suppressing of O2 concentration in UPW is very effective to suppress the increase of microroughness of Si(110) surface. The O2 concentration in UPW can be controlled by the ambient O2 concentration. Si(110) surface cannot be roughened when the O2 concentration is suppressed to less than 100 ppm in ambient (4 ppb in UPW) and the immersion time is less than 1 hour. It can be expected that the Si(110) surface flatness is maintained, and this surface is mainly used for the channel of FinFET. Furthermore, we demonstrated that the O2 concentration in a prototype 200-mm single-wafer cleaning chamber can be decreased to less than 100 ppm within 1 minute by an N2 purge of 200 l/min.

Control of large-scale vortices occurring in the semiconductor wafer cleaner

Control of large-scale vortices occurring in the semiconductor wafer cleaner

A New Approach to Tackle Wafer Contact Mark Contamination Issues in Marangoni Drying

Introduction Wafer drying is the last and critical step in wet wafer surface preparation processes for a product finished with clean and dry surfaces (1). Among various wafer drying technologies, Marangoni drying has been the most commonly used application nowadays due to its advantages in many aspects (1-3). However, surface tension gradients generated by Marangoni effect might not be able to fully overcome the capillary force existing at the tight geometry of the contact area between wafers and a wafer holder, resulting in contact mark contamination issues, especially under an inspection condition with reduced wafer edge exclusion (Figure 1). In this paper, we demonstrate the application of a technological approach to enhance a complete drainage of water droplets at the wafer/holder contact points to significantly mitigate the contact mark contamination issue. Experimental Experiments were conducted on a GAMATM wafer cleaning station in NAURA-Akrion’s Applications Lab, in which a LuCIDTM dryer is used for the wafer drying process. The dryer was set to run a typical Marangoni process at fixed parameters, with the in-tank wafer holder as the only variable. Various numbers of 200mm bare Si test wafers, sandwiched with clean dummy wafers to serve a full loading condition, were placed to various slots of a full pitch process carrier for a test batch. To ensure a consistent degree of hydrophilic state of Si surfaces during the drying process, each wafer batch was processed with an SC1/QDR/Dry instead of a Dry Only recipe. Before and after a process run, test wafers were inspected with a KLA-Tencor SP1 at ≥100nm particle threshold with 2mm edge exclusion. Results Wafer contact mark incidence was evaluated by overlapping the “pre” and “post” wafer map of each test wafer to identify the specific contact mark signature. Figure 2 highlights the incidence with respect to frequency and severity of contact mark occurrence. The former indicates how many test wafers in a testing batch show contact mark contamination, while the latter presents the extent of particle clustering in a contact mark. It can be seen from Fig.2 that both the frequency and severity of contact mark contamination were significantly reduced with appropriate liquid drainage at the contact area between the test wafers and a modified in-tank holder. Conclusion Experiments were conducted to tackle the wafer contact mark issue in a Marangoni drying process. The capillary effect holding liquid droplets at wafer/holder contact points can be overcome by a drainage technology to significantly reduce the contact mark incidence. With the technological solution, the Marangoni process window can be broadened and, in turn, the robustness and performance of the drying process are enhanced. References D.C. Burkman, et. al., in Handbook of Semiconductor Wafer Cleaning Technology (ed.. W. Kern), Noyes Publications, Westwood, NJ, 1993, pp. 131-134.A.F.M. Leenaars, et. al., Marangoni Drying: A New Extremely Clean Drying Process, Langmuir, 1990, 6 (11), pp. 1701-1703.T. Vukosav, Substrate Drying Using Surface Tension Gradient Technology, R&D Magazine, 7/16/2013. https://www.rdmag.com/article/2013/07/substrate-drying-using-surface-tension-gradient-technology Figure 1

Enhancing Post-Chemical Mechanical Planarization (CMP) Cleaning in the Presence of Polyelectrolyte-Based Chemistry Relevant to Shallow Trench Isolation

Semiconductor manufacturing relies on the synergistic effects of both chemical and mechanical processes to produce ultra-flat, defect free semiconductor wafers for integrated circuits (IC). Chemical mechanical planarization (CMP) is used to selectively target and remove the excess tetraethyl orthosilicate (TEOS) overburden on silicon substrates with slurries that contain diverse (surface adsorbing, pH adjusting, and rheology modifying) chemistry and nanosized ceria (CeO2) abrasives. A fundamental challenge for CeO2 based slurries is the required presence of the Ce3+ state to enhance removal, which is likely to remain on the wafer surface and increases the potential to induce defectivity such as scratching and particle contamination. Current industrial standards utilize a chemical desorption method, standard clean-1 (SC-1), that is comprised of concentrated ammonium hydroxide and hydrogen peroxide to convert the adsorbed particle to the less reactive Ce4+ state. While effective at removing particle contaminants, literature has shown that not all abrasives and defects are mitigated in the presence of SC-1. The focus of this work is to provide an alternative to traditional cleaning methods that balances chemical surface modification and mechanical removal to limit defects and irregularities on the wafer substrate. The formulated cleaning chemistry was evaluated under small-scale brush cleaning and soft pad/low down force buff polishing to clean polished wafers, which were processed with fluorescence microscopy to determine particle removal efficiency. Furthermore, atomic force microscopy (AFM) and friction measurements were utilized to investigate surface topography as a function of cleaning solution. In comparison to SC-1, the proposed cleaning chemistry shows an increased performance by reducing particle contamination and limiting surface defectivity.

A study of vortical structures occurring in a semiconductor wafer cleaner

A study of vortical structures occurring in a semiconductor wafer cleaner

In situ dry cleaning of Si wafer using OF2/NH3 remote plasma with low global warming potential

Dry cleaning technology is an essential technique that can be applied to remove native oxide and various contaminants during the semiconductor manufacturing for nanoscale electronic devices. In this study, the in situ dry cleaning of silicon dioxide (SiO2) with low global warming potential (GWP) gas mixtures has been investigated by sequential process steps composed of the reaction of SiO2 surface by oxygen difluoride (OF2) (GWP: <1)/ammonia (NH3) remote plasma and the removal of the reacted compound layer by lamp heating. By using the optimized OF2/NH3 (2:1) mixture for the surface reaction followed by the lamp heating at 200 °C to remove the reacted compound layer, a high-SiO2 cleaning rate and etch selectivity over silicon nitride (>30:1) could be obtained due to the formation of the highest HF concentration on the SiO2 surface at the OF2/NH3 (2:1) gas ratio. The compound layer formed during the reaction was (NH4)2SiF6 observed for a previously investigated NF3 (GWP: 17 200)/NH3 plasma, but the dry SiO2 cleaning rate and the etch selectivity over Si3N4 obtained by the OF2/NH3 plasma were higher than those by the optimized NF3/NH3 plasma. The effects of OF2/NH3 mixture dry cleaning on the electrical characteristics of metal-oxide-semiconductor (MOS) devices fabricated on the nano-scale trench patterned Si substrate with high aspect ratio were studied and compared with conventional wet and NF3/NH3 mixture dry cleaning-based devices. Compared with other cleaning methods, OF2/NH3 dry-cleaning shows the improved and reliable electrical characteristics such as sharper capacitance-voltage behavior, lower hysteresis, less interface trap charge and smaller contact resistivity. Therefore, it is believed that the in situ sequential dry SiO2 cleaning with the OF2/NH3 remote plasma can be applied as an essential cleaning method with extremely low GWP for fabricating next generation nano-scale devices.

Impact of Controlled Ni Contamination on Silicon Solar Wafer Material

Trace metal impurities are known to severely degrade the performance of silicon solar cells. The effect of Nickel dissolved in dilute cleaning solutions was studied in detail. Clean wafers were exposed to these mixtures.The resulting surface concentration and the effect on carrier lifetime upon thermal oxidation, were found to correlate with a first order relation to the concentration of Ni in the solution.The removal of Nickel from the surface by different cleaning recipes was evaluated and compared using thermal oxidation followed by carrier lifetime measurements.The resulting surface concentration and the effect on carrier lifetime upon thermal oxidation, were found to correlate with a first order relation to the concentration of Nickel in the solution.

Yield Enhancement due to Addition of Bevel Cleans at Middle of Line(MOL) Zone

As the technology nodes become smaller and smaller the circuit dies get closer and closer to the edge of the wafer. Defects and issues on the bevel are seen to cause issues such as flaking and blocked plating on the dies at the edge of the wafer. This drastically increases the need for a clean wafer edge as the issues directly translate to yield loss at the end of the line. The wafer edge and backside are shown to have a significant impact on yield as well as process variation [1]. Introducing a dilute HF and SC1 bevel clean at the MOL layer resolves flaking and defect issues found on the bevel. Dispensing it on the backside of the wafer and ensuring that the chemistry is rolled over to the bevel results in the backside of the wafer becoming cleaner and helps resolve overlay issues. All the above stated effects are seen to result in an overall edge gain in edge yield.

SiC Wafer Bonding and Deep Reactive Ion Etching Towards High-Aspect Ratio SiC MEMS Fabrication

Recent advances in SiC substrate quality and in the development of high aspect ratio reactive ion etching of SiC microstructures [1] have increased SiC fabrication feasibility and its potential for adaption in scalable optoelectronics [2] and microelectromechanical systems (MEMS). SiC is a wide band gap semiconductor that is suitable for high-power, high-temperature, highly reactive and mechanically strenuous environments. While the ability of SiC to withstand extreme conditions is desirable for harsh applications, it is this same durability that instigates restrictions or difficulties in SiC processing that are not present for Si; however, such process challenges do not outweigh the benefits of SiC. This work specifically tackles the processing challenges for SiC MEMS based on semiconductor-on-insulator structures. The importance of this topic can be viewed through the success of silicon-on-insulator (SOI); SOI wafers expanded the versatility of Si technology by enabling devices with increased switching speed and increased radiation hardness [3] as well as a platform for MEMS devices [4]. In the same vein, silicon carbide-on-insulator (SiCOI) wafers cast an even wider net, enabling SiC MEMS technology that leverages standard Si-based bulk micromachining processes [5] to produce unique device performance [6] and releasable microstructures [7]. However, in progressing towards monolithic SiC MEMS, feasible SiC wafer bonding techniques along with deep etching of high aspect ratio SiC microstructures is still needed to level the playing field between Si and SiC processing capabilities. In this work, the use of Si is avoided entirely and a high-yield wafer bonding and etch process of SiC/Insulator/SiC stacks is presented. The replacement of Si with SiC as a handle wafer allows for the design of all SiC-based MEMS devices for high shock resistant and temperature applications. The fabrication process begins with a thorough cleaning of 4H-SiC wafers followed by SiO2 deposition with a tetraethyl orthosilicate (TEOS) precursor via low-pressure chemical vapor deposition (LPCVD) at 750 °C. The oxide covered wafers were annealed to 1100 °C for 2 hours to densify and outgas the oxide. The SiO2 (up to 4 µm) on the Si-face was then chemically mechanically polished down to a final thickness of 3 µm thickness and a root-mean squared (RMS) roughness < 0.5 nm suitable for bonding (Figure 1). Prior to bonding, the wafers undergo additional cleaning processes to ensure a clean bonding interface. Direct wafer bonding of the Si faces of two SiC wafers was achieved in a class-100 cleanroom using a modified plasma bonding technique. The bonding was initiated by applying a local force to the center of the aligned wafers; the bond then propagates from the center to the wafer edge. Additionally, a post bond anneal at 1100 °C was used to achieve fusion strength. The bonded SiC wafers were electroplated with 1.7 - 2 μm Ni hard mask [1] and then diced into 10 mm x 10 mm coupons for anti-bosch etch experiments to produce deep SiC trenches [8]. An anti-bosch process describes a recipe that alternates between two SF6/O2 segments; one segment is designed to etch SiC, while the other segment is designed to remove sidewall passivation. This is contrary to the well-established Bosch process for Si which uses one segment to etch Si and the other to passivate the sidewalls. The anti-bosch process for SiC was designed to etch through the device layer and stop on the buried oxide; after which, the hard mask and seed metals were removed. Lastly, the etched microstructures were released with vapor hydrofluoric acid (HF). Figure 2 summarizes the process flow and Figure 3 shows the etch results achieved on 4H-SiC and 4H-SiC/SiO2/4H-SiC samples. The efficacy of the outlined process is demonstrated through successful actuation of fabricated structures (Figure 4). Overall, this work demonstrates a process for effective SiC wafer bonding and SiC etching in the presence of buried oxide in order to fabricate high-aspect ratio SiC MEMS. [1] L.E. Luna, et al. ECS J. Solid State Sci. Technol. 6, p. 207 (2017). [2] J.D. Caldwell, et al. Nano Lett. 13, p. 3690 (2013). [3] G.K. Celler and S. Cristoloveanu, J. Appl. Phys. 93, p. 4955 (2003). [4] E. Cook, et al. Solid-State Sensors, Actuators and Microsystems Workshop, June 2018. [5] R. Candler, et al. IEEE Transactions on Advanced Packaging 23, p. 227 (2003). [6] H-I. Kuo, et al. Proceedings of Transducers, Boston, MA, p. 742 (2003) [7] H.A. Moghadam, A. A. Orouji, A. Dideban, Semicond. Sci. Technol. 27, 015001 (2012). [8] L.E. Luna, et al. J. Micromech. Microeng. 27, 095004 (2017). Figure 1

Minimising total completion time on single-machine scheduling with new integrated maintenance activities

A single-machine scheduling problem with new maintenance activities is examined in this paper. In the scheduling literature, it is often assumed that the interval between maintenance activities is fixed or within a specified time frame. However, this assumption may not hold true in many real-world situations, such as the maintenance activities in wafer manufacturing of semiconductor. Before the wafer manufacturing process starts, it is imperative that the wafers go through a number of cleaning operations to avoid contamination. Using a cleaning agent as the main material of wafer cleaning, the contamination will be dissolved and removed from wafer surface. In case of contamination being accumulated substantial and going beyond a permitted value, the cleaning agent is highly likely to damage the wafer surfaces. Thus, the interval between maintenance activities in the wafer manufacturing process is deemed irregular. The objective function of the proposed problem is to minimise total completion time. Addressing the problem, a binary integer programming model is formulated in this paper. Furthermore, with the research problem being NP-hard, a heuristic based on two special properties is proposed to address the problem. To evaluate and validate the proposed heuristic, a new lower bound is further developed. Extensive experiments have been conducted showing that the proposed heuristic efficiently yields a near-optimal solution with an average percentage error of 15.4 from lower bound.

Probing the Interactions between CeO2 Nanoparticles and Cleaning Chemistry Relevant to Post STI CMP Cleaning

Fabrication of integrated circuits (IC) in the sub-micron regime utilizes shallow trench isolation (STI) to separate active circuits with a dielectric material, tetraethyl orthosilicate (TEOS). CMP is used to remove the excess TEOS layer to achieve planarity and expose the underlying structure without inducing defects. In an ideal system, the removal of TEOS is facilitated by colloidal suspensions (slurries) containing abrasive ceria (CeO2) nanoparticles and chemistry to produce defect free substrates. However, residual CeO2 particles can become embedded at the interface leading to defects impacting device performance. Current industrial methods of removing particles use Standard Clean-1 (SC-1), incorporating concentrated NH4OH and H2O2 to chemically remove organic contaminants and abrasive particles. This work set out to investigate particle encapsulation using novel polyelectrolyte and surfactant based chemistry to enhance electrostatic repulsions that occur at the interface during post-CMP cleaning. In-situ studies utilizing dynamic light scattering and turbidity measurements have provided insight regarding the role of polyelectrolyte and surfactant concentration during the cleaning process. The formulated cleaning chemistry was evaluated under small scale brush cleaning to clean polished TEOS wafers, which were then processed with fluorescence microscopy to determine particle removal efficiency. Analogous to SC-1, the cleaning chemistry shows comparable particle removal; however at an increased efficiency, making it a viable alternative to traditional cleaning methods.

Numerical Study of the Flow in the Semiconductor Wafer Cleaner by OpenFOAM

Numerical Study of the Flow in the Semiconductor Wafer Cleaner by OpenFOAM