Circuit Specifications Research Articles

Audible circuit noise in hearing aid amplifiers.

Audible electronic circuit noise generated within a hearing aid is distracting to a listener in quiet situations and, if the noise level is high enough, may cause listener irritation and rejection of the hearing aid. Thus for hearing aid specification and fitting purposes, it is useful to know the acoustic levels at which this internal noise may become audible and also at which it may become objectionable. For hearing aid amplifier circuit specification and design purposes, it is useful to know the same levels in electrical terms. This paper reports on a study that used an amplifier with no acoustic input and a hearing aid receiver output to simulate internally generated hearing aid circuit noise. Results are reported for testing eight subjects with high-frequency hearing loss for the perceived acoustic and electrical levels at which internal circuit noise became both audible and objectionable.

Measurement of crosstalk-induced delay errors inintegrated circuits

Coupling between lines may cause a variation in the effective transition delay in a digital signal path if there exists a simultaneous transition in the coupled lines. The authors present a measurement method for this effect, using a specifically designed integrated circuit. It is shown that the effect may produce either an increase or a decrease in the critical path, therefore altering the maximum frequency specification of a synchronous sequential circuit.

Design of layered ridge dielectric waveguide for millimeter and sub-millimeter wave circuits

Design rules for Layered Ridge Dielectric Waveguide (LRDW) are presented for the first time through simple figures and closed form equations. The Effective Dielectric Constant (EDC) method is used to develop the design rules that account for typical circuit specifications such as higher order mode suppression, dispersion, attenuation, and coupling between adjacent transmission lines. Comparisons between the design of LRDW, image guide, and millimeter-wave dielectric ridge guide are made.

The synthesis of compact fuzzy neural circuits

Concerns Smart Parts, a class of fuzzy neural hardware. Smart Parts are "smart" in that they can learn an input-output mapping implicit in a data set. They are "parts" in that they are small high-speed fuzzy neural processors meant to provide the fuzzy hardware designer customized functionality in a small package. They are application-specific. The paper focuses on the tool assisting this synthesis, TROUT. Using design heuristics that favor small size and high speed, TROUT can produce Smart Parts circuit specifications virtually automatically. It starts by minimizing the complexity of the target application data set in a way that simplifies the eventual implementation. It chooses a neural net or fuzzy network model from a small library that best suits the data set. In this paper, we detail the fuzzy min-max classifier model (FMM). TROUT optimizes FMM learning parameters to produce the smallest circuit offering the highest input vector throughout. Two architectural insights make the synthesis tractable. First, the FMM network architecture is structurally adaptive. Second, asynchronous circuit-design techniques are used because they simplify the synthesis process by eliminating clock scheduling. The output from TROUT is very high-level hardware description language (VHDL) code that can be used to synthesize the circuit in any of a number of circuit technologies. We outline the synthesis process and provide a circuit example based on the public domain wine classification data set.

A unified signal transition graph model for asynchronous control circuit synthesis

Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses. Our aim is to fill exactly this gap, offering both low-level (analysis-oriented) and high-level (specification-oriented) models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the two levels. One interesting side result is the precise characterization of classical static and dynamic hazards in terms of our model. Consequently the designer can check the specification and directly decide if the behavior of any implementation will depend, e.g., on the delays of the signals described by such specification. We also outline a design methodology based on our models, pointing out how they can be used to select appropriate high and low-level models depending on the desired characteristics of the system.

A hyper optimal encoding scheme for self-checking circuits

A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs [log(r+1)] check bits, where r is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the hidden m-out-of-n code words. The hidden m-out-of-n code words are found when all unique output patterns, specified by the circuit specification, in the n selected output bits have exactly m 1s. The output bits that belong to the hidden m-out-of-n code words are then excluded from further encoding. Typically, the number of added check bits of the proposed technique ranges from 0 to [log(p+1)], where p/spl les/r. When hidden m-out-of-n code words exist, applying the proposed scheme usually results in significant hardware cost and delay time reduction. In the five MCNC FSM benchmark circuits that have been identified with hidden m-out-of-n code words, 10% to 41% hardware reductions are exhibited compared to the theoretically optimal separable code encoding scheme. In addition, 7% to 45% reductions in checking delays are demonstrated for the same circuits compared to the separable code encoding scheme.

Worst-case analysis and optimization of VLSI circuit performances

In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by first computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to find an optimal design point at which all of the circuit specifications are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multicriteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and efficiency. >

Computer-aided selection of components for technology-independent specifications

The specification of a synchronous circuit can be given as a set of abstract building blocks that are interconnected. A set of fast algorithms are presented here for the selection of components that map each of these abstract building blocks to one of a number of suitable physical components. The first set of algorithms select the set of fastest or cheapest (smallest area) of all possible components. Another set of algorithms is given that will find a solution with user-defined constraints. These algorithms, which are implemented as part of the SPOT system, use a exhaustive list of timing information to increase the likelihood of a good solution. >

A correctness criterion for asynchronous circuit validation and optimization

In order to reasonably determine the correctness of asynchronous circuit implementations and specifications, Dill (1989) has developed a variant of trace theory. Trace theory describes the behavior of an asynchronous circuit by representing its possible executions as strings, called "traces." A useful relation defined in this theory is called conformance, which holds when one trace specification can be safely substituted for another. We propose a new relation in the context of Dill's trace theory, called strong conformance. We show that this relation is capable of detecting certain errors in asynchronous circuits that cannot be detected through conformance. Strong conformance also helps to justify circuit optimization rules where a component is replaced by another component having extra capabilities (e.g., it can accept more inputs). The structural operators of Dill's trace theory-compose, rename, and hide-are shown to be monotonic with respect to strong conformance. Experiments are presented using a modified version of Dill's trace theory verifier that implements a check for strong conformance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Aggregation of Evidence in a Fuzzy Knowledge-Based Method for Automated Tuning of Microwave Electric Circuits

The electric circuit tuning process, which requires manual tuning of a set of trimmers by the human operators, was automated through the application of a fuzzy knowledge-based system. In a complex tuning process, multiple circuit specification criteria had to be simultaneously satisfied by several trimmers. The main objective of this study was to examine different tuning evidence aggregation methods in order to reduce the overall circuit tuning time. In the proposed fuzzy knowledge-based system, the effect of each trimmer on each tuning criterion was expressed by a grade of the fuzzy membership related to each circuit output. The overall effect of each trimmer on the circuit tuning performance was modeled by an aggregation of the grades used for trimmer selection. The model simulation results showed that the geometrical average operator was the best method for evidence aggregation. To compensate for the lack of fuzzy rules, some heuristic rules were also introduced to adjust the aggregated evidence values. It was shown that these rules significantly improved the performance of the tuning system. Finally, it was observed that although the tuning rules were elicited from human experts, it was not essential in this study to emulate the human's information aggregation processes. This was due to the fact that in the manual tuning process the human aggregation of evidence about circuit performance did not necessarily provide the best solution for the intended task.

An industry-sponsored professional development course: design for automotive ASICs

Delco Electronics Corporation developed and offered a two week professional development course on integrated circuit (IC) design entitled "Design for Automotive ASICs" during the summer of 1991. It was cosponsored with the American Society for Engineering Education, with additional training and support provided by Mentor Graphics, Cascade Design Automation and Hewlett Packard Corporations. During the first week, engineers and managers from Delco Electronics described products and technologies through several presentations and tours. Also, the participants learned about IC design tools and methodology through lectures and labs using engineering workstations. During the second week the participants designed one of four ICs based on circuit specifications for automotive applications. Our experiences in the planning and execution of this course can provide guidance for others considering the development of an industry-sponsored course.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS

Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

Analysis of signal probability in logic circuits using stochastic models

Analyzes the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classification of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type being determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows one to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits are given. >

Anatomy of the Stirling Engine Cycle

Conditions are isolated for thermodynamic processes in two Stirling cycle machines to be identical. The conditions form the basis for the concept of ‘functional similarity’. Using the similarity conditions the designer may scale the detailed gas circuit specification of a viable Stirling engine to a derivative design of different size, crankshaft speed, working fluid and pressure. The method complements, and provides an independent check of, the simulation approach to gas circuit design.

An automata-theoretic approach to behavioral equivalence

Formal verification methods are used in the integrated circuit design process to guarantee equivalence between circuit specifications and implementations at the same or differing levels of abstraction. Equivalence checking between two finite-state automata or two combinational logic circuits is precisely defined and supported by a body of theoretical work. Algorithms that can determine the equivalence of large sequential and combinational logic circuits exist, and are in use today. In contrast, verifying that a logic-level description correctly implements a behavioral specification is considerably less developed. One major hindrance toward a precise notion of behavioral verification has been that parallel, serial or pipelined implementations of the same behavioral description can be implemented in finite-state automata with different input/output behaviors. In this paper, we use ϵ-moves to model the degree freedom that is afforded parallelism in a behavioral description that also contains complex control. Given some assumptions, we show how the set of finite automata derivable from a behavioral description can be presented compactly as an input-programmed automaton ( p-Automaton). The p-Automaton is named such due to the fact that during its derivation, we program meta-input variables in the p-Automaton that are not present in the original description. The logic-level implementation is deemed to be equivalent to the behavioral description if and only if the p-Automaton is equivalent to the logic-level finite automaton under some assignment to the meta-input variables. The above method allows for extending the use of finite-state automatan equivalence-checking algorithms to the problem of behavioral verification. It is particularly useful for verifying descriptions with a moderate amount of parallelism and complex control. We present experimental results obtained using our approach.

Asynchronous design for programmable digital signal processors

A systematic procedure for designing fully asynchronous programmable processors from an architectural description is described. Design issues such as pipelining, interconnection circuit specifications, data flow control, program flow control, feedback and initialization, I/O (input/output) interface, and processor architecture are discussed. The system-level tradeoffs of using synchronous design versus asynchronous design are addressed. Simulation results of an asynchronous version of a commercial digital signal processor are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Manufacturing Automation and Prototyping for Printed Wiring Boards

This paper presents an improved method of manufacturing automation and prototyping for Printed Wiring Boards. The protocol requires that three data sources be present [circuit specifications, component specifications, and a circuit layout database], in computer interpretable form. The specifications for these three data stores is presented and a generic workcell, suitable for low volume high part mix prototyping is discussed. In order for the protocol to control the generic workcell, the subtask orders which are required for proper function are also presented and discussed.

GM-learn: an iterative learning algorithm for CMOS gate matrix layout

In the paper, an iterative CMOS gate matrix layout algorithm utilising artificial intelligence (A.I.) learning techniques is proposed. This algorithm, called GM-Learn, features a rudimentary learning mechanism which enables iterative improvements of the quality of a gate matrix layout. This is accomplished through the repetitive applications of a one-pass gate matrix layout algorithm, called GM-Plan, to realise a given circuit specification. The function of GM-Learn, is then to ‘learn’ to modify the heuristics used in GM-Plan based on the previous trials. Two AI learning paradigms, known as rote learning and learning by parameter adjustment, are employed. These learning techniques enable GM-Learn to modify its heuristic search parameters based on information obtained from previous iterations. Benchmark test results indicate that this novel algorithm is able to produce a high quality gate matrix layout in only a few iterations. The significance of this new method is that it may be applicable to other combinatorial VLSI physical design problems where heuristic guided search is required.

The set theory of arithmetic decomposition

The set theory of arithmetic decomposition is a method of designing complex addition/subtraction circuits at any radix using strictly positional, sign-local number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation. The order in which and weight at which each operator is applied maps directly to a physical implementation, including both multiple-level logic and connectivity. The method is readily automated, and has been used to design some higher radix arithmetic circuits. It is possible to compute the cost of a given adder before the detailed design is complete.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accurate and convenient evaluation method of magnetic field

An evaluation method for the magnetic field employed in an MRI (magnetic resonance imaging) system is described. In the past, the magnetic-field distribution was approximated by a linear combination of spherical harmonics, and the coefficients were used for the evaluation of the field homogeneity. The accuracy of the evaluation method presented is demonstrated by comparisons between field distributions computed from the coefficients and measurements. The results give an estimate for the number of coefficients needed for a good approximation. The contour map computed in this way conveniently given the field distribution from measurements at only a few points. The image distortion estimated from the field distribution is demonstrated to be a valuable index for evaluating the specification of the magnetic circuit in an MRI system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>