Abstract
A systematic procedure for designing fully asynchronous programmable processors from an architectural description is described. Design issues such as pipelining, interconnection circuit specifications, data flow control, program flow control, feedback and initialization, I/O (input/output) interface, and processor architecture are discussed. The system-level tradeoffs of using synchronous design versus asynchronous design are addressed. Simulation results of an asynchronous version of a commercial digital signal processor are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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