An automata-theoretic approach to behavioral equivalence

Abstract

Formal verification methods are used in the integrated circuit design process to guarantee equivalence between circuit specifications and implementations at the same or differing levels of abstraction. Equivalence checking between two finite-state automata or two combinational logic circuits is precisely defined and supported by a body of theoretical work. Algorithms that can determine the equivalence of large sequential and combinational logic circuits exist, and are in use today. In contrast, verifying that a logic-level description correctly implements a behavioral specification is considerably less developed. One major hindrance toward a precise notion of behavioral verification has been that parallel, serial or pipelined implementations of the same behavioral description can be implemented in finite-state automata with different input/output behaviors. In this paper, we use ϵ-moves to model the degree freedom that is afforded parallelism in a behavioral description that also contains complex control. Given some assumptions, we show how the set of finite automata derivable from a behavioral description can be presented compactly as an input-programmed automaton ( p-Automaton). The p-Automaton is named such due to the fact that during its derivation, we program meta-input variables in the p-Automaton that are not present in the original description. The logic-level implementation is deemed to be equivalent to the behavioral description if and only if the p-Automaton is equivalent to the logic-level finite automaton under some assignment to the meta-input variables. The above method allows for extending the use of finite-state automatan equivalence-checking algorithms to the problem of behavioral verification. It is particularly useful for verifying descriptions with a moderate amount of parallelism and complex control. We present experimental results obtained using our approach.