Circuit Layout Research Articles

Displacement-reconstruction-realized components by structure-sensing integration via a hybrid 3D printing strategy

Realizing displacement reconstruction is one of the main goals of real-time intelligent monitoring systems, motivating a highly promising requirement for structure-sensing integration technology. To obtain displacement-reconstruction-realized components, the crucial challenges cover the whole process including sensor-layout design, sensor assembly and rapidly functional verification. Accordingly, a rapid iterative solution is proposed from sensor-layout optimization to structure-sensing integrated fabrication then to displacement-reconstruction realization. A sensor array is optimally designed with minimized unit number and simplified circuit layout to integrate on the surface of or embed into the structures. Then we combine the direct-ink-writing with fused deposition modeling, achieving hybrid 3D printing strategy to fabricate the structure-sensing integrated components within one step. The local strains of plates are detected by the sensors and their full-field displacements are then reconstructed without any loading information. This work provides insights into the design and fabrication of structure–function-integration structures or devices.

Design of T-shaped non-uniform microstrip lines for reducing crosstalk in high-speed PCBs

High-speed and high-density PCB circuit layout design faces serious signal integrity problems. Crosstalk is one of the key problems affecting signal quality. Periodic non-uniform differential microstrip lines have the possibility of reducing crosstalk. This paper proposes a T-shaped non-uniform microstrip line, which adds the T-shaped bump on the inner side of the parallel microstrip lines. The microstrip line adopts the minimum batch production process linewidth to maintain high density, which is suitable for occasions where the line spacing is three times the linewidth. The principle of crosstalk mitigation for T-shaped microstrip lines is explained, and the evolution process of T-shaped microstrip lines is given, compared with parallel microstrip lines and tabbed lines with the same density. The simulation resulting in the time domain and frequency domain shows that the transmission performance of the T-shaped microstrip line is good, and crosstalk can be effectively suppressed in a high-frequency band, even better in some specific frequencies due to the crosstalk fluctuation with frequency.

Design of the cryogenic loop for the superconducting toroidal-field magnets of the Divertor Tokamak Test

The design of the cryogenic circuit for the toroidal field magnets has a relevant role in the overall costs of the DTT cryogenic plant (or cryoplant), hence numerical tools can be useful to investigate and to compare different configurations for the TF cooling circuit in support of the selection of the most suitable one. The system-level cryogenic circuit module of the validated thermal–hydraulic 4C code is adopted in this work to model the DTT TF cooling system. At first, the model of the reference circuit layout is implemented and simulated during the plasma pulsed operation of the DTT machine, highlighting the necessity to reduce the heat load transferred to the refrigerator due to the large power consumption of the cold compressor. In view of the above, different TF circuit layouts and optimization strategies are presented, including mitigation strategies for the smoothing of the peak heat load to the refrigerator, leading to a reduction of the cold compressor power up to the 66% with respect to that computed for the reference TF cryogenic circuit layout.

A Toolbox for Designing 3D‐Printing‐Ready Pneumatic Circuits for Controlling Soft Robots

The robotics field has witnessed a rapid increase in the popularity of soft pneumatic robots due to their adaptability to unstructured environments and safe human–robot interaction. However, many of them are still controlled by rigid solenoid valves and microcontrollers. Recent research works have introduced various electronics‐free computational devices for soft robotic applications. Yet, connecting these individual components into pneumatic circuits still remains challenging. The manual circuit design, fabrication, and piping process can bring inefficient circuit layout, redundant tubing, unreliable fittings, and potentially human mistakes. This work presents an open‐source toolbox for automatically designing pneumatic circuits for soft robotic applications. The toolbox takes the desired computation function along with some space constraints as inputs, and generates a 3D‐printable file of a pneumatic circuit that can be fabricated and used directly. This is achieved by efficiently positioning the logic gates and air channels while considering the workspace constraints, fabrication limits, material cost, and system complexity. The versatility of the design automation algorithm has been tested with two different truth tables and six different workspaces. The work also showcases utilizing the toolbox to design a computational circuit that governs the movements of a soft robotic hand with four pneumatic actuators.

Design analysis of a multi-port 8-shaped inductor for RF applications

Portable wireless devices with a high-frequency range should also function with low voltage, providing low power dissipation and noise. Design engineers cannot successfully meet the above design objectives without using RF inductors. Since integrated inductors are an essential part of RF circuits, these devices are highlighted because of their enormous size in the circuit layout and unsettling radiations. As a result, there is a solid motivation to design, optimize, and model inductors made on Si substrates. This article presents the design of a multi-path multi-port 8-shaped inductor with dimensions of 150 × 150 μm, simulated using Cadence EMX simulator to analyze its Q-factor and inductance. The analysis provided that the simulated inductance has the highest value of 12.2 nH, which is the maximum value across all the conclusions of this research. Another significant discovery was that this Inductor is suitable for up to 45 GHz. To achieve an improved frequency of operation for the multi-path, multi-port 8-shaped Inductor, an analysis of the Inductor’s topology is conducted, focusing on enhancing the loop widths of metal layers and optimizing spacing between the metal tracks.

Sequential Laser-Burned Lignin and Hydrogen Evolution-Assisted Copper Electrodeposition to Manufacture Wearable Electronics.

In the contemporary world, wearable electronics and smart textiles/fabrics are galvanizing a transformation of the health care, aerospace, military, and commercial industries. However, a major challenge that exists is the manufacture of electronic circuits directly on fabrics. In this work, we addressed the issue by developing a sequential manufacturing process. First, the target fabric was coated with a customized ink containing lignin. Next, a desired circuit layout was patterned by laser burning lignin, converting it to carbon and establishing a conductive template on the fabric. At last, using an in-house-designed printer, a devised localized hydrogen evolution-assisted (HEA) copper electroplating method was applied to metalize the surface of the laser-burned lignin pattern to achieve a very low resistive circuit layout (0.103 Ω for a 1 cm long interconnect). The nanostructure and material composition of the different layers were investigated via scanning electron microscopy, energy-dispersive X-ray spectroscopy (EDX), Raman spectroscopy, and Fourier-transform infrared spectroscopy (FTIR). Monitoring the conductivity change before and after bending, rolling, stretching, washing, and adhesion tests presented remarkable mechanical stability due to the entanglement of the copper nanostructure to the fibers of the fabric. Furthermore, the HEA method was used to solder a light-emitting diode to a patterned circuit on the fabric by growing copper at the terminals, creating interconnects. The presented sequential printing method has the potential for fabricating reliable wearable electronics for various applications, particularly in medical monitoring.

Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO2Transistors

The operating characteristics of MOS transistors, such as the switching speed and power consumption, have been improved due to the increased reduction of the lateral dimensions. A further advantage of modern scaled nodes is that defects within the oxide and at the semiconductor/oxide interface are observed in a reduced number, however, they show an enhanced impact on the device characteristics. This leads to a substantially increased variability of the threshold voltages, sub-threshold swing, and carrier mobility when comparing nominally identical devices. As a consequence of this pronounced device-to-device variability, statistical analyses are required for studying the reliability of these technologies. By performing measurements on large sets of devices, statistical distributions of defect properties can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. In this work, the distributions of the contributions of defects on the device behavior are investigated, by making use of commercial pMOS and nMOS devices. The combined use of single-defect extractions and the defect-centric model (DCM) enables us to accurately extract valuable information for a whole technology. While existing approaches focus on either large-area or nanoscale nodes, our results hold for both regimes and are of high relevance for accurately describing the impact of charge traps which is mandatory for further improvement of the layout and performance of circuits.

GNN-Based Hierarchical Annotation for Analog Circuits

Analog designs consist of multiple hierarchical functional blocks. Each block can be built using one of several design topologies, where the choice of topology is based on circuit performance requirements. A major challenge in automating analog design is in the identification of these functional blocks, which enables the creation of hierarchical netlist representations. This can facilitate a variety of design automation tasks such as circuit layout optimization because the layout is dictated by constraints at each level, such as symmetry requirements, that depend on the topology of the hierarchical block. Traditional graph-based methods find it hard to automatically identify the large number of structural variants of each block. To overcome this limitation, this paper leverages recent advances in graph neural networks (GNNs). A variety of GNN strategies is used to identify netlist elements for circuit functional blocks at higher levels of the design hierarchy, where numerous design variants are possible. At lower levels of hierarchy, where the degrees of freedom in circuit topology are limited, structures are identified using graph-based algorithms. The proposed hierarchical recognition scheme enables the identification of layout constraints such as symmetry and matching, which enable high-quality hierarchical layouts. This method is scalable across a wide range of analog designs. An experimental evaluation shows a high degree of accuracy over a wide range of analog designs, identifying functional blocks such as low-noise amplifiers, operational transconductance amplifiers, mixers, oscillators, and band-pass filters in larger circuits.

Direct-Ink-Writing Printed Strain Rosette Sensor Array with Optimized Circuit Layout

The full-field multiaxial strain measurement is highly desired for application of structural monitoring but still challenging, especially when the manufacturing and assembling for large-area sensing devices is quite difficult. Compared with the traditional procedure of gluing commercial strain gauges on the structure surfaces for strain monitoring, the recently developed Direct-Ink-Writing (DIW) technology provides a feasible way to directly print sensors on the structure. However, there are still crucial issues in the design and printing strategies to be probed and improved. Therefore, in this work, we propose an integrated strategy from layered circuit scheme to rapid manufacturing of strain rosette sensor array based on the DIW technology. Benefit from the innovative design with simplified circuit layout and the advantages of DIW for printing multilayer structures, here we achieve optimization design principle for strain rosette sensor array with scalable circuit layout, which enable a hierarchical printing strategy for multiaxial strain monitoring in large scale or multiple domains. The strategy is highly expected to adapt for the emerging requirement in various applications such as integrated soft electronics, nondestructive testing and small-batch medical devices.

Fully inkjet-printed dual-mode sensor for simultaneous pressure and temperature sensing with high decoupling

Pressure-temperature dual-mode sensors have been attracting much attention for their various potential applications in areas such as human–computer interaction and health monitoring. However, it is still a challenge to construct an all-in-one dual-mode sensor on a flexible substrate through a simple process. Herein, a flexible dual-mode sensor based on the pressure-capacitance sensitivity of porous polydimethylsiloxane (PDMS) and the temperature-resistance sensitivity of reduced graphene oxide (rGO) film has been fabricated. The dual-mode sensor not only owns an excellent pressure sensing capabilities with ultra-wide detection range (0–1000 kPa), a low-pressure detection limit (2.5 Pa), a fast response time (40 ms) and a high cyclic stability (10,000 cycles), but also can accurately distinguish a temperature change of 0.2 °C. In addition, theoretical formulas are successfully developed to explain the causes of signal crosstalk. Effective decoupling is achieved according to the mechanistic analysis, and the detected capacitance and resistance signals are converted into the actual pressure and temperature. Furthermore, a dual-mode sensor array is fabricated by fully inkjet printing method that incorporate the structure of the dual-mode sensor unit and the circuit design of shared electrodes to reduce the complexity of circuit layout for multi-position detection. Besides, a pressure-temperature alarm system is constructed using this dual-mode sensor to monitor different environmental changes. Based on its superior sensing performance and decoupling capabilities, the sensor has great potential in multifunctional synchronous sensing scenarios.

An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling

In this paper, we propose an analog circuit building block generator, which is composed of a layout-aware analog circuit sizing scheme and an automated analog circuit layout generator. We reformulate the analog circuit sizing problem as a novel constrained multi-objective optimization problem and propose a multi-objective Bayesian optimization scheme that can find multiple different qualified designs. We further leverage a nested multi-fidelity Bayesian optimization method in layout-aware sizing to counterbalance the schematic-level simulation and the expensive post-layout simulation without losing efficiency. The automated layout generator enables the in-loop layout generation, and thus it is possible to find a set of valid post-layout results directly. The experimental results on three real-world analog circuits have demonstrated the efficiency of our proposed approach.

SLIM Tricks: Tools, Concepts, and Strategies for the Development of Planar Ion Guides.

Traveling wave ion mobility experiments using planar electrode structures (e.g., structures for lossless ion manipulation, TW-SLIM) leverage the mature manufacturing capabilities of printed circuit boards (PCBs). With routine levels of mechanical precision below 150 μm, the conceptual flexibility afforded by PCBs for use as planar ion guides is expansive. To date, the design and construction of TW-SLIM platforms require considerable legacy expertise, especially with respect to simulation and circuit layout strategies. To lower the barrier of TW-SLIM implementation, we introduce Python-based interactive tools that assist in graphical layout of the core electrode footprints for planar ion guides with minimal user inputs. These scripts also export the exact component locations and assignments for direct integration into KiCad and SIMION for PCB finalization and ion flight simulations. The design concepts embodied in the set of scripts comprising SLIM Pickins (PCB CAD generation) and pigsim (SIMION workspace generation) build upon the lessons learned in the independent development of the research-grade TW-SLIM platforms in operation at WSU. Due to the inherent flexibility of the PCB manufacturing process and the time devoted to board layouts prior to manufacturing, both scripts serve to enable rapid, iterative design considerations. Because only a few predefined parameters are necessary (i.e., the TW-SLIM monomer width, x position following a TW Turn, and y position following a TW Turn) it is possible to design the exact component layouts and accompanying simulation space in a manner of minutes. There is no known limitation to the board layout capacities of the scripts, and the size of a designed layout is ultimately constrained by the abilities of the final PCB design and simulation tools, KiCad and SIMION, to accommodate the thousands of electrodes comprising the final design (i.e., RAM and software overhead). Toward removing the barriers to exploring new SLIM tracks and the likelihood of layout errors that require considerable revision and engineering time, the SLIM Pickins and pigsim tools (included as Supporting Information) allow the user to quickly design a length of planar ion guide, simulate its abilities to confine and transmit ions, compare hypothetical board outlines to given vacuum chamber dimensions, and generate a near-production ready PCB CAD file. In addition to these tools, this report outlines a series of cost-saving strategies with respect to vacuum feedthroughs and vacuum chamber design for TW ion mobility experiments using planar ion guides.

3D SRAM Macro Design in 3D Nanofabric Process Technology

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

Modelling of Bi-Directional Buck-Boost Converter for Electric Vehicle

Abstract: The rapid growth of electric vehicles (EVs) has necessitated the development of efficient and versatile energy storage systems. In this study, we present the modelling and implementation of a switching bi-directional buck-boost converter based on electric vehicle hybrid energy storage. The proposed converter offers a flexible and reliable solution for managing energy flow between different storage elements in an EV, such as batteries and ultra-capacitors. First, a comprehensive mathematical model of the converter is developed, taking into account the dynamic behaviour of the energy storage components. This model enables us to analyse and optimize the converter's performance in terms of efficiency, voltage regulation, and power delivery capabilities. Furthermore, simulation studies are conducted to validate the accuracy of the model and assess the converter's performance under various operating conditions. Based on the modelling and simulation results, a practical implementation of the converter is carried out using high-quality electronic components. The design considerations, including component selection, circuit layout, and control strategy, are discussed in detail. The implemented converter is then evaluated experimentally to validate its performance and verify the effectiveness of the proposed modelling approach. The results demonstrate that the switching bidirectional buck-boost converter effectively manages the energy flow between the different storage elements in the hybrid energy storage system. It achieves high conversion efficiency, voltage regulation, and power transfer capabilities, enhancing the overall performance and range of electric vehicles. The developed model and implementation provide valuable insights for the design and optimization of similar converter topologies for electric vehicle applications. Overall, this study contributes to the advancement of energy storage systems in electric vehicles, facilitating the adoption of sustainable and efficient transportation solutions in the future

Analysis on optimal length scale of thermoelectric generators when using different circuit layouts

Using thermoelectric generators (TEGs) to recover waste heat is a potential technological approach. To achieve maximum thermoelectric conversion power, scale optimization of thermoelectric modules has been reported in previous studies. However, the results obtained were all based on numerical calculations, and the analytical solution could not be proven theoretically. Therefore, understanding of the internal mechanism of the structural optimization theory is limited. In addition, the relevant optimization results were based on a full-series circuit, and no structural optimization theory for other circuit types has been proposed. To fill this gap, this study adopts a method that combines theoretical derivation and numerical calculation. First, the analytical solution of the optimal scale is derived by taking the full series as an example, and the existence of an optimal structure of the thermoelectric modules is theoretically confirmed. Subsequently, the scale optimization performance of the thermoelectric structure based on different circuit structures was further analyzed, providing theoretical guidance for the optimization of the thermoelectric structure under different circuit connection modes. The results indicate that the optimal lengths for different circuit layouts are quite different, regardless of whether maximum total power or net power is used as the optimization objective. However, for convenience, the optimal length of the full-series circuit mode can be used to design a constant length for all types of multi-stage series circuit modes when the objective is to maximize the net power output. Using this method, the percentage deviation of the obtained power from its theoretical peak net power can be less than 0.6% for the example presented in this study.

A Comparative Analysis of Doherty and Outphasing MMIC GaN Power Amplifiers for 5G Applications.

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC's 100 nm GaN-on-Si technology (D01GH). After a theoretical analysis, the design and layout of both circuits are presented. The DPA uses an asymmetric configuration where the main amplifier is biased in class AB and the auxiliary amplifier is biased in class C, while the OPA uses two amplifiers biased in class B. In the comparative analysis, it has been observed that the OPA presents a better performance in terms of maximum power added efficiency (PAE), while the DPA provides higher linearity and efficiency at 7.5 dB output back-off (OBO). At a 1 dB compression point, the OPA exhibits an output power of 33 dBm with a maximum PAE of 58.3% compared to 44.2% for the DPA for an output power of 35 dBm, and at 7.5 dB OBO, the DPA achieves a PAE of 38.5%, while the OPA achieves 26.1%. The area has been optimized using absorbing adjacent component techniques, resulting in an area of 3.26 mm2 for the DPA and 3.18 mm2 for the OPA.

Symmetric Circuit Layout With Decoupled Modular Switching Cells for Multiparalleled SiC mosfets

Parallel connection of silicon carbide (SiC) metal-oxide-semiconductor transistors (MOSFETs) are widely used in large-current-capacity applications or power modules. However, current imbalance caused by the tolerance of device parameters or asymmetric circuit layout is still a challenge for the reliability of the paralleled devices. The asymmetry of power circuit layout is inevitable when more than two devices are paralleled, which will lead to serious dynamic current imbalance. In this paper, an equivalently symmetric power circuit layout based on decoupled paralleled modular switching cells (MSCs) is presented. The current sharing mechanisms of typical asymmetric power circuit layouts are firstly illustrated. The layout with distributed DC decoupling capacitors turns out to have the potential to modify the current paths but requires further optimization. Based on the mechanisms, the construction of the symmetric layout with the concept of MSC is elaborated by mathematical analysis. DC decoupling capacitors are used to decouple the paralleled symmetric MSCs. Thereafter, the key considerations for the decoupling capacitors are discussed. Experiments are finally carried out to validate the analysis. The test results show that the peak current imbalance is reduced to only 4.1% by the equivalently symmetric power circuit layout, which confirms the effect of decoupled MSCs method.

Chemical mechanical planarization for Ta-based superconducting quantum devices

We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at a 300 mm wafer scale. This work has established the elements of various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum circuits. The fabrication of these structures utilizes a 193 nm optical lithography along with 300 mm process tools for dielectric deposition, reactive ion etch, wet-clean, CMP, and in-line metrology—all tools typical for a 300 mm wafer CMOS foundry. Theprocess development was guided by measurements of the physical and electrical characteristics of the planarized structures. Physical characterization such as atomic force microscopy across the 300 mm wafer surface showed that local topography was less than 5 nm. Electrical characterization confirmed low leakage at room temperature, and less than 12% within wafer sheet resistance variation for damascene Ta line widths ranging from 100 nm to 3 μm. Run-to-run reproducibility was also evaluated. Effects of process integration choices including the deposited thickness of Ta are discussed.

Optimization of holes routing in hydraulic manifold blocks based on simulated annealing algorithm

The design of the hydraulic manifold block is time-consuming, laborious, and prone to make mistakes due to the vertical intersection and dense complexity of its internal oil passage network. The mathematical optimization model of this problem is given based on the comprehensive analysis of the structural characteristics and design rules of the internal orifices of the hydraulic manifold block. Using the integrated circuit layout algorithm for reference, an optimization design method of a multi-wire mesh channel network based on routing sequence optimization is proposed and verified by an example. The research results show that the optimization of the connection order between multiple wire networks at both ends and the routing order between multiple wire networks in a single-wire network can not only achieve the optimal design of the connectivity of the single-wire network but also ensure the optimal connectivity result of the entire hole network. At the same time, as the bottom core algorithm of the integrated block layout optimization design, it can provide a powerful technical guarantee for improving the integrated block design level, quality, and automation.

Simulating quantum circuits using tree tensor networks

We develop and analyze a method for simulating quantum circuits on classical computers by representing quantum states as rooted tree tensor networks. Our algorithm first determines a suitable, fixed tree structure adapted to the expected entanglement generated by the quantum circuit. The gates are sequentially applied to the tree by absorbing single-qubit gates into leaf nodes, and splitting two-qubit gates via singular value decomposition and threading the resulting virtual bond through the tree. We theoretically analyze the applicability of the method as well as its computational cost and memory requirements, and identify advantageous scenarios in terms of required bond dimensions as compared to a matrix product state representation. The study is complemented by numerical experiments for different quantum circuit layouts up to 37 qubits.