An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling

Abstract

In this paper, we propose an analog circuit building block generator, which is composed of a layout-aware analog circuit sizing scheme and an automated analog circuit layout generator. We reformulate the analog circuit sizing problem as a novel constrained multi-objective optimization problem and propose a multi-objective Bayesian optimization scheme that can find multiple different qualified designs. We further leverage a nested multi-fidelity Bayesian optimization method in layout-aware sizing to counterbalance the schematic-level simulation and the expensive post-layout simulation without losing efficiency. The automated layout generator enables the in-loop layout generation, and thus it is possible to find a set of valid post-layout results directly. The experimental results on three real-world analog circuits have demonstrated the efficiency of our proposed approach.