Low-power Circuit Applications Research Articles

Skyrmion Sensor-Based Low-Power Global Interconnects

In this paper, we propose the use of magnetic skyrmion sensors for low-voltage, low-current global interconnects. Magnetic skyrmions have shown great potential for low-power circuit applications, since skyrmions can be generated and moved by remarkably low-current pulses. We propose the use of skyrmion-based current sensors at the receiver that allows low-current signal transmission through the line. The proposed skyrmion sensor consists of a magnetic nanotrack on top of a spin-Hall metal (SHM). The skyrmion is nucleated in the nanotrack by using spin-polarized current and, subsequently, moved along the nanotrack by using a charge current through the SHM. This charge current is the input current from a global interconnect line, which moves the skyrmion depending on the logic input to the line. The resistance of a magnetic tunnel junction (MTJ) at the receiver is based on the movement/location of the skyrmion. This resistance change is sensed using a reference MTJ and a simple complementary metal–oxide–semiconductor (CMOS) inverter. Such a receiver configuration acts as a built-in latch, and hence, expensive voltage converters or transimpedance amplifiers can be avoided, which are the bottlenecks in a conventional low-power interconnect design. Our simulation results indicate that for a 10 mm Cu-line in 45 nm CMOS technology, the energy consumption with skyrmion-based sensing is $\sim 50\times $ lower compared with full swing and $\sim 25\times $ lower compared with low-swing CMOS interconnect.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents.

Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/μm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/μm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.

Sharp Switching Characteristics of Single Electron Transistor with Discretized Charge Input

For the low-power consumption analog and digital circuit applications based on a single-electron transistor, enhancement of its switching performance is required. Our previous works analytically and numerically demonstrated that a discretized charge input device, which comprised a tunnel junction and two capacitors, improved the gain characteristics of single-electron devices. We report the design and fabrication of an aluminum-based single-electron transistor having the discretized charge input function. Flat-plate and interdigital geometries were employed for adjusting capacitances of grounded and the coupling capacitors. The sample exhibited clear switching on input-output characteristics at the finite temperature.

New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications.

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

Sandwich double gate vertical tunneling field-effect transistor

In this work, a sandwich vertical tunnel field effect transistor (SDG-VTFET) is presented and studied. Since the dominant carrier tunneling of SDG-VFET occurs in a direction that is in line with the gate field, high ON-state current and steep subthreshold slope are observed. Comparisons between SDG-VFET and double gate tunnel field effect transistor are made to clarify advantages of SDG-VTFET. The simulation results of our work show that SDG-VTFET has stronger gate control, steeper subthreshold slope and higher ON-state current. The device plays a promising candidate for future low power circuit applications.

Asymmetric dual-gate tunneling FET with improved performance

In this work, we propose and simulate an asymmetric dual-gate tunneling FET (ADG-TFET) combining a tunneling field effect transistor (TFET) with a junctionless field effect transistor (JLFET). The current is controlled by an in the bottom channel potential barrier as well as the reverse-biased P+ pocket-Intrinsic region (p-i) tunnel junction bandgap, which combines the merits of both bandgap-controlled TFET and barrier-controlled JLFET. The simulation results of ADG-TFET with high-κ dielectric material (HfO2) of 40-nm gate length show excellent characteristics with high ION/IOFF ratio of 3.3 × 1010 and ION of 302 μA/μm, a steep subthreshold slope (SS) for point SS of 35 mV/decade and average SS of 54 mV/decade at room temperature, which indicates that ADG-TFET is a promising candidate for future low power circuit applications.

Adhesion Limits and Design Criteria for Nanorelays

Microelectromechanical switches are of interest for low-power circuit applications due to their minimal OFF state leakage current. This paper uses 22-nm CMOS fabrication technology and the clamped cantilever geometry as the basis for establishing design rules for electrostatic nanorelays and estimates the design parameters needed for nanorelay actuation. The adhesive pull-off force of various substrate/cantilever combinations is simulated using molecular dynamics with a force field that parameterizes van der Waals interactions, and measured using atomic force microscopy. Both methods show that for the substrates studied, H-passivated Si produces the least adhesive surface with adhesive pressure close to the critical pressure required for pull-out. Experimental results quantifying adhesion and electrical current conduction show that it is impossible to simultaneously meet the adhesion and current conduction requirements of a nanorelay. We show that contact adhesion is the key parameter limiting the scalability of electromechanical relays at the nanoscale.

New Assessment Methodology Based on Energy–Delay–Yield Cooptimization for Nanoscale CMOS Technology

A new technology assessment methodology is proposed to simultaneously evaluate circuit-level energy, delay, and yield under realistic device operation theme through Monte Carlo analysis. Given any yield constraints, this new methodology can maximize the circuit energy efficiency without overdesign. It provides a method to quantify the tradeoff between energy–delay (ED) and yield. The proposed method is proved to be efficient especially for low power circuit applications compared with ED-only approach. Taking 14-nm FinFET design, for example, the impacts of major variation sources are analyzed for different circuit applications, showing a different trend from the ED-only approach. In addition, the methodology is also extended to include the impacts of reliability issues. A desired design strategy is found to balance the design merits and circuit reliability. The proposed methodology is helpful for technology assessment and early stage circuit design and planning.

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-<inline-formula> <tex-math notation="TeX">$\kappa $ </tex-math></inline-formula>/Metal Gate

We present a vertical gate-all-around Si nanowire (SiNW) metal–oxide–semiconductor field-effect transistor with high- \(\kappa \) dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal–oxide–semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with \(I_\mathrm{{\scriptstyle ON}}\) /I \(_\mathrm{{\scriptstyle OFF}}\) > \(10^{4}\) , subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for \(4F^{2}\) cross-point memory cells.

Ultra-low voltage MEMS switch using a folded hinge structure

Abstract An ultra-low voltage microelectromechanical system (MEMS) switch for low-power integrated circuit (IC) applications is proposed, fabricated and demonstrated. The folded hinge structure allows a large beam structure to be suspended with a designed air gap, effectively suppressing unwanted deflection. The actuation voltage of the switch was measured to be 1.7 V, the lowest among electrostatic switches. There was no variation in the actuation voltage until 106 cyclic actuations, showing the stability of a low actuation voltage in electrostatic actuation for the first time. The contact resistance was around 12 Ω, caused by a low contact force below 1 μN despite an Au–Au contact.

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.

Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications

Design & Analysis of A Charge Re-Cycle Based Novel Lphs Adiabatic Logic Circuits for Low Power Applications

A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology

The low-flicker noise (1/f noise) gate-controlled lateral-vertical bipolar junction transistor array (GC-LV-BJTA) is developed with a foundry's 55-nm CMOS technology for low-noise and low-power RF circuit applications. The GC-LV-BJTA is formed by paralleling some unit cells into an array structure for sharing adjacent collectors and bases, thus minimizing the total area. Many efforts, including the use of a deep n-well, a novel layout, an optimized emitter perimeter/area ratio, and a negatively biased gate, have been implemented to suppress the noise level and enhance the current gain. As a result, the GC-LV-BJTA, consisting of 16 unit cells with a 0.16-μm gate length, achieves a high gain of 85.7 with available low 1/f noise level, as compared with the nMOS or SiGe HBT.

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

A comparative study on analog/RF performance of UTB GOI and SOI devices

In this paper, a comprehensive comparison of analog/RF performance of ultra-thin-body (UTB) GOI and UTB SOI devices is investigated through simulation. Analog/RF figures of merit of GOI and SOI devices are estimated including gm/Id values, intrinsic gain (gm/gd), cutoff frequency (fT), maximum oscillation frequency (fMAX) and intrinsic delay (CV/I). The results show that GOI devices exhibit great gain performance enhancement over SOI devices. Besides, fT and fMAX of GOI devices are also higher than those of SOI devices. Furthermore, GOI devices show strong potential for low-power circuit applications since their advantages over SOI devices are more remarkable biasing at low operating voltages. The results demonstrate that GOI devices exhibit improved analog/RF scaling capability and are suitable for low-voltage, low-power analog/RF circuit applications.

Characteristics of an InP ∕ InGaAs Double Heterojunction Bipolar Transistor with an InAlGaAs ∕ InP Composite Collector Structure

The characteristics of an interesting double heterojunction bipolar transistor (DHBT) with an composite collector structure were demonstrated and studied. Experimentally, the operation regime was wider than 11 decades in magnitude of collector current density . As compared to previous reports, the studied device exhibited a relatively larger Early voltage, smaller base-collector reverse saturation current, , smaller multiplication factor, M-1, and smaller electron impact ionization, α. Moreover, the device studied also showed a relatively weaker temperature dependence on the electron impact ionization, α. Consequently, the DHBT device offers promise for low-voltage and low-power circuit applications.

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in the header/footer device and provides a wide range of virtual ground (GND) or supply voltage. Physical analysis and numerical mix-mode device/circuit-simulation results confirm that the proposed scheme can be applied to low-power high-performance circuit applications in 65-nm technology node and beyond. Variable/dynamic supply or GND voltage using the proposed scheme improves read and write margins in scaled SRAM without degrading read and write performance.

On the Temperature-Dependent Electron Impact Ionizations in a Step-Graded InAlGaAs∕InP Collector Double Heterojunction Bipolar Transistor

The temperature-dependent electron impact ionizations of an InP/InGaAs double heterojunction bipolar transistor (DHBT) with a step-graded InAlGaAs/InP collector structure are studied and demonstrated from 300 to 400 K. Experimentally, the multiplication factor and electron ionization coefficient are increased with increasing temperature. Furthermore, the studied device shows a lower multiplication factor and weaker temperature dependence as compared with conventional InP/InGaAs HBTs. Therefore, the studied DHBT device with a step-graded InAlGaAs/InP collector structure provides promise for low-voltage and low-power circuit applications.