Delay and Power Evaluation of Negative Capacitance Ferroelectric MOSFET Based on SPICE Model

Abstract

The current evaluation on negative capacitance ferroelectric MOSFET (NC-FeFET) mostly reports device-level current/capacitance-voltage prediction and approaches with ease of integration in SPICE for circuit level performance prediction are very limited. For benchmarking against intrinsic MOSFET and beyond-CMOS devices, a new Landau–Khalatnikov theory-based SPICE model of ferroelectric is presented as a series connection of a voltage controlled voltage source and a resistor. It predicts both static and dynamic behaviors by including ferroelectric damping constant. Integration of this ferroelectric model with BSIM4 model of 45-nm CMOS technology allows prediction of circuit-level performance of NC-FeEFT. In current–voltage characteristics, both subthreshold swing and off-state current are reduced compared with intrinsic MOSFET. For an inverter chain, different values of damping constants give rise to a wide range of propagation delays and power consumptions. Only NC-FeFET using sufficiently low damping constant ferroelectric with similar response time to intrinsic MOSFET can be considered as a low-power device with a similar propagation delay. In this case, its dynamic power is suppressed by the same proportion as that of internal voltage amplification and static leakage power also drops. Our results reveal the ferroelectric switching time and Landau parameter requirements for FeFET use in low-power circuit applications.