Asymmetric dual-gate tunneling FET with improved performance

Abstract

In this work, we propose and simulate an asymmetric dual-gate tunneling FET (ADG-TFET) combining a tunneling field effect transistor (TFET) with a junctionless field effect transistor (JLFET). The current is controlled by an in the bottom channel potential barrier as well as the reverse-biased P+ pocket-Intrinsic region (p-i) tunnel junction bandgap, which combines the merits of both bandgap-controlled TFET and barrier-controlled JLFET. The simulation results of ADG-TFET with high-κ dielectric material (HfO2) of 40-nm gate length show excellent characteristics with high ION/IOFF ratio of 3.3 × 1010 and ION of 302 μA/μm, a steep subthreshold slope (SS) for point SS of 35 mV/decade and average SS of 54 mV/decade at room temperature, which indicates that ADG-TFET is a promising candidate for future low power circuit applications.