Circuit Design Issues Research Articles

Does the operating point of a series-parallel network of monotone resistors satisfy all resistor ratings?

An important issue in circuit design is whether every element operates within its rated values. For the particular case of a series-parallel network of monotone resistors (i.e., one ports) whose characteristic curves are continuous and monotonically increasing, at least within the ranges between their rated values, we present a rapid procedure for resolving this question. If at least one resistor operates outside of its ratings, our procedure will reveal this fact without having to determine the operating point of the entire network, or even of that resistor alone. On the other hand, if all elements operate within their ratings, our procedure ascertains that as well, while again avoiding a computation of the operating point of the entire network. This procedure can also be applied to series-parallel subnetworks N/sub SP/ of an arbitrary network N/sub S/P but now it can only reveal whether N cannot have a within-ratings operating point because N/sub SP/ does not have one.

Electrical Design Techniques for MCM-D

The electrical environment facing the MCM-D designer is rather different from that presented by MCM-C or MCM-L technology. In many respects the MCM-D environment is preferable: dielectric constants are low, electrical lengths of vias are very short, wiring is denser and hence wiring lengths are shorter, and high-capacitance integral power supply decoupling can be provided. However, MCM-D sheet resistances are higher and linewidths narrower, with the result that signal interconnects are clearly 'R-L-C' transmission lines (contrasted with the 'L-C' lines of MCM-Lor the 'R-C' lines on an IC chip). Also, the close spacing of chips on an MCM-D substrate implies that the capacitive loading on a net is not negligible compared with the net's self-capacitance. These differences imply the need for different design techniques from those used on PC boards, to achieve optimal performance. For example, the time honoured 50 £1 impedance line is often not the preferred structure in a performance-optimised MCM-D design. This paper addresses electrical circuit design issues which are unique to MCM-D technology. Other very important MCM-D design issues (not covered in this work) include system-level partitioning strategies and optimisation (vertically integrated design), design for testability, thermal design and mechanical packaging issues.

An evaluation system for distributed-time VHDL simulation

Performance of VHDL simulation is a critical issue in electronic circuit design and is hard to achieve due to the complexity of the language and the different abstraction levels. This paper presents a system for performance evaluation of distributed-time VHDL simulation based on the analysis of simulation traces. The system allows to model different architectures, interconnection topologies and simulation algorithms. The main tools are a VHDL analyzer to extract dependencies, and a trace-driven simulator to evaluate the execution time on a given architecture.

Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

A single flux quantum logic gate with high functionality

The D-gate is a quantum flux parametron (QFP) logic gate which was proposed to reduce input interaction and improve input margin. It is basically a 2-input multiplexer with two select signals. By giving appropriate inputs, a single gate can also perform 2-input AND, 2-input OR, 2-input XOR, 3-input majority, 3-input parity or 1-bit equality. Since it is a QFP device, it has a self-latching effect which can be exploited for pipelined designs of many combinational logic functions. However, because QFP logic is a clocked logic expected to operate at 10 GHz or more, propagation delay becomes an important issue in circuit design.

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion

A 200-MHz 11-tap finite-impulse-response (FIR) digital filter for compensating the sin(x)/x spectrum distortion introduced by digital-to-analog (D/A) converters was designed and fabricated in a 1- mu m CMOS technology. The chip core area is 1.91*3.28 mm/sup 2/ and its complexity is approximately 14,000 transistors. A fully parallel bit-level pipelined transpose-form carry-save architecture using simple powers-of-2 coefficients was used to achieve high throughput and low complexity. The various tradeoffs involving architecture selection, circuit design, and timing issues are presented, and the difficulties in realizing the speed potential of bit-level pipelined circuits are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A linear statistical FET model using principal component analysis

An important issue in statistical circuit design, other than the algorithms themselves, is the development of efficient, statistically valid element models. The authors first discuss what features are needed for a good statistical model. The standard FET model is shown to be difficult to use in a statistical simulation, due to the nonlinear relation between FET S-parameters and model parameters. A linear statistical FET model is then proposed that is based on principal component analysis. This linear model gives uncorrelated model parameters. In an example using measured S-parameter data from ninety 0.5- mu m GaAs FETs, 13 uncorrelated model parameters were needed to model the data from 1 to 11 GHz and at one bias. Simulation using this linear model and issues relating to bias are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design Issues in the ISDN U-Interface Transceiver

The design challenges faced in the integrated circuit realization of the basic customer access U-interface transceiver at 144 kbits/s in the integrated services digital network (ISDN) are summarized. Given the cost and performance objectives, this represents a very challenging design problem from an algorithmic and technology point of view. This survey paper describes the alternative design approaches concentrating on algorithmic issues as opposed to circuit design issues, in the context of the echo cancellation (EC) method of full duplex data transmission. Particular emphasis is given to the areas of echo cancellation, equalization, line code selection, and timing recovery.