Abstract
A 200-MHz 11-tap finite-impulse-response (FIR) digital filter for compensating the sin(x)/x spectrum distortion introduced by digital-to-analog (D/A) converters was designed and fabricated in a 1- mu m CMOS technology. The chip core area is 1.91*3.28 mm/sup 2/ and its complexity is approximately 14,000 transistors. A fully parallel bit-level pipelined transpose-form carry-save architecture using simple powers-of-2 coefficients was used to achieve high throughput and low complexity. The various tradeoffs involving architecture selection, circuit design, and timing issues are presented, and the difficulties in realizing the speed potential of bit-level pipelined circuits are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Published Version
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