Electrical Design Techniques for MCM-D

Abstract

The electrical environment facing the MCM-D designer is rather different from that presented by MCM-C or MCM-L technology. In many respects the MCM-D environment is preferable: dielectric constants are low, electrical lengths of vias are very short, wiring is denser and hence wiring lengths are shorter, and high-capacitance integral power supply decoupling can be provided. However, MCM-D sheet resistances are higher and linewidths narrower, with the result that signal interconnects are clearly 'R-L-C' transmission lines (contrasted with the 'L-C' lines of MCM-Lor the 'R-C' lines on an IC chip). Also, the close spacing of chips on an MCM-D substrate implies that the capacitive loading on a net is not negligible compared with the net's self-capacitance. These differences imply the need for different design techniques from those used on PC boards, to achieve optimal performance. For example, the time honoured 50 £1 impedance line is often not the preferred structure in a performance-optimised MCM-D design. This paper addresses electrical circuit design issues which are unique to MCM-D technology. Other very important MCM-D design issues (not covered in this work) include system-level partitioning strategies and optimisation (vertically integrated design), design for testability, thermal design and mechanical packaging issues.