Circuit Board Level Research Articles

Reliability Thermal Design, Simulation and Experimental Verification of Electronic Monitoring Unit for Magnetic Resonance System

The monitoring unit used in the nuclear magnetic resonance system, as an important unit of the system, faces a high thermal risk during its entire life cycle. This paper ensures the high efficiency and reliability of the thermal design of the product module from the two dimensions of structural design and device derating design. In order to reduce the risk of thermal design of electronic modules and comprehensively verify the effectiveness of thermal design of electronic modules, the design verification is carried out by combining simulation and experiment. In the simulation process, by establishing a thermal simulation model at the circuit board level, the crustal temperature of the core device is numerically calculated, and the index is compared with the thermal design index value and the test value, on the one hand, to verify the correctness of the simulation model. On the other hand, the validity of thermal design is verified. In the testing process, a thermal test platform for product modules is built, and the thermal characteristics test values of the core components of the module under extreme electrical conditions are obtained, and the corresponding conversion methods are used to predict the thermal performance and thermal design margin of the product at different altitudes. The results show that the electronic module can meet the thermal design requirements in terms of structural design and derating design of core components, and can ensure that the product module can work safely and reliably during the entire life cycle of the NMR system.

A Practical Technique Using Planar Coils to Make the Radiated Immunity of Specific Integrated Circuit Pins Less Dependent From PCB Orientation

In this article, an inexpensive passive approach is proposed, both making the immunity of integrated circuits (ICs) less dependent on their orientation and controlling the immunity of specific pins. This technique is based on the introduction of planar 2-D coils surrounding the microcontroller ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\mu }$</tex-math></inline-formula> C) at the printed circuit board (PCB) level. The importance of the coil physical parameters (geometry, resonant frequency, and orientation) as well as the interference frequency is investigated, evaluating the difference in the magnetic field at the pin of interest in two opposite orientations (i.e., 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> and 180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> ). The effectiveness of the proposed technique is demonstrated in full-wave simulations and measurements, showcasing the provided immunity improvement through monitoring the behavior of the sensitive pins. Besides, this article strongly recommends IC designers not to place power supply pins close to the corners of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\mu }$</tex-math></inline-formula> C package due to the presence of the highest local tangential magnetic field when no structures are implemented. Coil orientation is shown to be the key adjustment parameter to enhance the immunity of any specific pin. The resonant frequency of the coils is found to be less relevant than its geometry and distance with respect to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\mu }$</tex-math></inline-formula> C pins. The proposed technique using the octagonal coils was also found to be effective in a wide frequency range (from 210 to at least 500 MHz). Compared to a no-coil case, an immunity enhancement of 74.2% (27.5%) is achieved in measurement (simulation) by the addition of an octagonal coil to the PCB, which clearly demonstrates the relevance of that simple approach for practical use in highly sensitive integrated electronics.

Validation of IC Conducted Emission and Immunity Models Including Aging and Thermal Stress

Environmental factors, such as aging and thermal stress, can seriously impact the electromagnetic compatibility behavior of an integrated circuit (IC). The standardized IC emission model for conducted emission (ICEM-CE) and IC immunity model for conducted immunity (ICIM-CI) can be used in industry to predict electromagnetic behavior at the IC and the printed circuit board level. However, these do not take into account the effect of aging and extreme temperature variations. In this article, a custom IC designed in silicon-on-insulator technology, containing several independent analog blocks, is used to characterize the influence of aging and temperature on conducted emission and immunity through measurements and transistor-level simulations. The highly accelerated temperature and humidity stress test (HAST) was performed to evaluate aging and its influence on IC parameters. The results show that the passive distribution network is only influenced by thermal stress and not HAST aging. The latter mainly affects the active elements in the IC and reduces the conducted emission and immunity levels through intrinsic permanent degradation mechanisms. Furthermore, thermal stress mainly causes drifts in the transistor characteristics (such as threshold voltage and effective mobility), which affect the conducted emission and immunity levels and resulting in soft failures. All drifts/tolerances collected from measurements and simulations are characterized in a way that makes it possible to include them in potential future versions of the ICEM-CE and ICIM-CI standards.

NMR instrumentation- a primer

This primer covers de-bugging NMR hardware, at the level of major components (not the circuit board level). It is intended for users of NMR who are unlikely to build their own spectrometer, but will need to localize the malfunction to individual small sub-systems. Brand names and some part numbers of appropriate test equipment and lab-gadgets are given. But many users will find themselves in need of special purpose NMR probes, so construction of a dedicated probe is not beyond consideration. Thus, simple single-resonance probe circuits are discussed at greater length. The need for tuning and coupling of the probe tuned circuit is treated as an exercise in impedance matching.

On the Correlation Between Near-Field Scan Immunity and Radiated Immunity at Printed Circuit Board Level – Part II

The work presented in this two-part paper focuses on a prediction method of the radiated susceptibility of integrated circuit and printed circuit board from near-field scan injection, in order to anticipate risks of noncompliance due to design weakness. In Part I, a worst-case estimator of the far-field induced voltage on a PCB trace was proposed. Based on it, an estimator of the radiated susceptibility of a printed circuit board based on near-field scan results is derived and validated through two validation case studies.

On the Correlation Between Near-Field Scan Immunity and Radiated Immunity at Printed Circuit Board Level – Part I

Near-field (NF) scan immunity is a powerful technique to identify the root-cause of failures produced during radiated immunity (RI) tests at the integrated circuit and printed circuit board (PCB) levels. However, a prediction method of the RI level from NF scan immunity results is still lacking. This type of method would help board designers to anticipate risks of RI noncompliance related to PCB directly after an NF scan campaign. This two-part article addresses this issue. In the first part, the equivalence between far-field (FF) and NF coupling on a microstrip line is discussed in order to derive an estimator of the FF induced voltage from NF scan results.

Evaluation of Cost-Effective Flexible High-Speed Data Exchange Links for Heterogeneously Integrated Multi-Chip Modules and Boards

With increasing complexity and heterogeneity, miniaturized integrated system on both multi-chip module and printed circuit board levels relies more and more on high-speed point-to-point serial signal transmission links as the backbone of inter-chip data signal exchange network, which are inevitably accompanied by signal integrity problems such as loss, reflection, and crosstalk. The difficulties in the physical design phase of interconnect routing for high-speed link on densely occupied package interposers or printed circuit boards and the associated planar area overhead (keep-out zone for the crosstalk prevention and impedance matching, etc.), as well as the relevant cost in manufacturing, performance analysis and actual measurement or evaluation, are also sharply increasing; furthermore, the interconnects implemented on interposer or printed circuit board substrate are physically inflexible, and the corresponding microsystems are not suitable for emerging applications that generally demand good deformability and good conformality to 3-dimensionally shaped mounting surface. How to simultaneously elevate the cost-effectiveness, signal transmission performance and physical flexibility of the high-speed link, while keeping low profile of the whole module, has become one of the major challenges in the evolution of micro/nano system technology. Accordingly, this paper proposes a cable-based point-to-point link method, which adopts physically flexible and widely available off-the-shell cables that can be assembled onto the surface of the interposers or boards as a potential cost-effective solution to the challenge mentioned above. Universal Serial Bus, micro-coaxial cables, and Twinax cables are explored as candidates. The full links for each cable, from one of the paired connectors to another, are physically modeled and validated by an electromagnetic full-wave structural simulation tool, with key components of each type of link taken into considerations. The simulated results and the measured results from vector network analyzers are compared, which verifies the effectiveness of our proposal.

On the use of Magnetically Coupled Resonant Snubbers to Mitigate the Electromagnetic Emission of Power Switching Circuits

This letter presents a novel solution to attenuate the electromagnetic emission of power switching circuits due to the resonance of the loop parasitic inductances with the parasitic capacitances of the power devices. A resonant snubber based on the magnetic coupling of a power parasitic loop causing unwanted oscillations with another one inserted at the printed circuit board level purposely and loaded by a dissipative element, is presented. A design method is proposed and used to damp the unwanted oscillations affecting the switching voltage and current in a prototype, which was specifically designed and fabricated to validate the proposed solution. The conducted emission delivered by such a prototype equipped with the resonant snubber, with an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> snubber, and without any snubber are compared.

A two‐turn loop active magnetic field probe design for high sensitivity near‐field measurement

This paper develops an active magnetic near field probe (H-field probe) by using a four-layer printed circuit board (PCB) technique. Two-turn detection structure and a low noise amplifier are used to improve probe's frequency response. The two-turn detection structure can maximize the use of PCB stack resources, and a 14.5 dB gain amplifier can increase signal output capability. The probe can then be used for electromagnetic compatibility (EMC) test from 150 kHz to 3 GHz. Compared with traditional active shielded-loop H-field probe (TAHP) with loop area of 500 μm 2 , the frequency response of the proposed probe can improve 20 dB at 0.5 GHz. Different from the method of comparing the sensitivity of the probe only through the frequency response, this paper measures and analyzes the real sensitivity of the probing device composed of the proposed probe. Under the condition of the same receiver parameter setting, the sensitivity at 0.5 GHz is increased by 11.7 dB compared with commercial passive probing device and 20.2 dB at 0.5 GHz compared with the probing device with TAHP device. It reaches −32.4 dB μA. In addition, the proposed probe has acceptable spatial resolution of 1.28 mm at 1 GHz, which is more suitable for printed circuit board level EMI analysis.

Frequency response mismatch calibration in 2-channel time-interleaved oscilloscopes.

The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.

Physics of Failure (PoF) Based Lifetime Prediction of Power Electronics at the Printed Circuit Board Level

This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.

Analytical Models of Passive Linear Structures in Printed Circuit Boards

Analytical models for passive linear structures, like metallic traces, vias, are proposed for simulations at the package and Printed circuit board (PCB) levels. In the proposed method, traces are modeled based on the transmission line theory, whereas the vias are described by the parallel-plate impedance and several equivalent circuits elements. The proposed models can be applied to efficiently simulate composed passive linear structures. Several scenarios are analyzed including traces with two or three width, traces routed into different layers and interconnects commonly used in PCBs. The results of the models are compared with those from the fullwave simulations and experiments. An improvement on the computation speed has been observed with respect to the full-wave simulations at the effective range of models. In our measurements, a compensation approach of impedance mismatch in parameter measurements is analyzed and calculated, which could significantly simplify the experimental process.

IEEE Standard P2716 Update: Characterization of the Effectiveness of Printed Circuit Board Level Shielding

At the IEEE EMC and EMC Europe Symposia in 2013, the idea was raised to continue the work that had been started by IEEE 299 and IEEE 299.1 around the characterization of the shielding effectiveness (SE) of enclosures. IEEE 299–2006 (“IEEE Standard Method for Measuring the Effectiveness of Electromagnetic Shielding Enclosures”) covers enclosures having all dimensions greater than or equal to 2.0m. IEEE 299.1 (“IEEE Standard Method for Measuring the Effectiveness of Electromagnetic Shielding Enclosures”) covers enclosures and boxes having all dimensions between 0.1 m and 2 m. The question raised in 2013 was if there was interest in and need for an IEEE standard on the characterization of the effectiveness of shielding enclosures with even smaller sizes. As a side effect, the question on whether an IEEE standard around the characterization of the SE of planar materials was needed as no such guidance document was available at the time.

ESD Diode Protection Incorporated on Leadframe Package

With the new die technology becomes smaller and thinner, silicon die circuit metallization also becomes smaller, thus electronic devices like quad-flat no-leads multi-row (QFN-mr) semiconductor leadframe package design become more sensitive and prone to electrostatic discharge (ESD) damages. This paper focused and introduced an additional surface mount technology by attaching diodes before and after diebonding process to protect the whole package and to prevent package related issues encountered. With this diode attached on the silicon die and leads, added protection could be achieved on the integrated circuit (IC) mounted on the circuit board level.

Analysis and Design of a Low-Cost Well-Performance and Easy-to-Design Current Sensing Circuit Suitable for SiC mosfets

Current sense resistor (CSR) is widely used due to cost and integration considerations in industrial applications. However, when CSRs are used to sense transient currents caused by power device switching, especially fast-switching silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets) with high di/dt, even a tiny parasitic inductance in CSRs bring a significant impact on its sensing performance. This article proposes a low-cost well-performance and easy-to-design current sensing circuit that uses the CSRs and an LR compensation network (LRCN) to compensate for the effect of parasitic inductance on transient current sensing. In order to support the parameter selection of the LR network, the effects of parameters such as parasitic capacitance, parasitic inductance, and loads on the performance of the proposed current sensing circuit are analyzed in detail. Meanwhile, a parasitic inductance measurement method that only needs passive probes is proposed to measure and calculate the parasitic inductance of CSRs. This circuit can not only sense the transient current on the printed circuit board level but also observe the transient current on the oscilloscope through a coaxial cable connection. Finally, experimental studies under an inductive load double pulse test setup with SiC mosfets are carried out to verify the validity and feasibility of the proposed transient current sensing circuit. Only a high self-resonant frequency inductor and a surface mounted device resistor are needed to form the LR network to fully compensate the effect of parasitic inductance on CSRs.

Hardware Trojan Detection on a PCB Through Differential Power Monitoring

There is a general consensus that contemporary electronics are at risk of cyber-attacks or malicious modifications, such as Hardware Trojans (HT). This makes it crucial to develop reliable countermeasures at both Integrated Circuit (IC) and Printed Circuit Board (PCB) levels. While HT detection at IC level has been widely studied in the past several years, there is still very limited research carried out to tackle HTs on PCBs. We propose a power analysis method for detecting HT components implanted on PCBs. An experimental setup, using a hardware prototype, is built and tested for verification of the methodology, taking process and temperature variations into account. The results confirm the ability to detect alien components on a PCB and provide directions for further research. The performance degradation of the original PCB due to the implementation of the proposed approach is negligible. The area overhead of the proposed method is small, related to the original PCB design, and consists of Sub Power Monitors of individual ICs on the PCB and Main Power Monitor for the overall power measurement of the PCB. To the best of our knowledge this research is the first to develop a PCB HT detection methodology using power analysis.

Miniaturized Polarization Insensitive Metamaterial Absorber Applied on EMI Suppression

This paper presents the analysis and design of a miniaturized polarization insensitive metamaterial absorber (MMA) for suppression of the electromagnetic interference (EMI) at microwave frequency range. The proposed MMA consists of a periodic array of double split ring structures printed on an FR4 substrate with a thickness of 0.07 λ 0 . The simulated results derived from CST indicate that the absorption ratio of the MMA is over 90% with a wide frequency range from 8.3 GHz to 11.3 GHz for a normal incident electromagnetic (EM) wave. To understand the EM wave absorption mechanism, an equivalent circuit model of the MMA unit cell is constructed to investigate the absorbing characteristics, and the electric field and surface current distributions are analyzed at absorption peaks.. Both equivalent circuit model (ECM) and measured results show good agreement. What's more, the measurement data shows that the radiated electric field of the patch antenna at 1 meter is significantly reduced at 10 GHz while loading with the MMA. A maximum suppression of 18 dBμν/m is achieved at 10 GHz. As the proposed absorber possesses good ability on electromagnetic radiation absorption, it could be well applied on printed circuit board (PCB) level EMI suppression.

Bringing the SEED Approach to the Next Level: Generating IC Models for System ESD and Electrical Stress Simulation out of Design Data

System-level electrostatic discharge (ESD) robustness design according to ISO10605 or IEC 61000-4-2 on printed circuit board (PCB) level is still a challenge). The blocking point is often the lack of accurate models of complete integrated circuits (ICs). Previously published methodologies to generate ESD models for ICs are all based on measurements of the complete IC, showing the drawback of complex, difficult and time-consuming measurements. This paper proposes a novel methodology to generate ESD models for complete ICs out of their design data. The proposed approach requires no measurements with the complete IC and hence can reduce the effort significantly. Furthermore, the methodology offers the possibility for automation, which further reduces the number of needed resources. It is based on the approach of black box modeling. This means simplified behavioral models are used, which contain solely the characteristic behavior in case of disturbance pulses. The methodology focuses on the transient behavior as well as the physical destruction limits of smart power products. Behavioral model in this context means the transient response due to disturbance pulse in terms of voltage drops and current drain. The procedure is explained and verified step by step on an exemplary product. It can be easily transferred to other products. System designers receive a powerful model for targeting certain robustness of their system against transient disturbances. Further enhancements of the methodology can enable also the soft failure assessment by simulation.

Notice of Retraction: Extension of the Unmatched-Media Time Reversal Method to Locate Longitudinal Soft Defects in Transmission Lines

This paper applies the electromagnetic time reversal method to the identification of the location and to the quantification of the impedance Zd of longitudinal defects along transmission lines. A closed-form expression for the time-reversal current transfer function is derived. This new transfer function benefits from the same properties of that for solid or soft transversal faults, and hence, can be used for locating the defects along the line. Different scenarios are considered ranging from power lines to signals channels for high-speed digital systems at printed circuit board and package level. The results are discussed and used to assess the accuracy and scalability of the proposed method.

A New Methodology for EMC Prediction of Integrated Circuits After Aging

Electromagnetic compatibility (EMC) of integrated circuits (ICs) represents a major constraint for the qualification of electronic circuits. Today, there exist standardized models such as integrated circuit emission model for conducted emissions (ICEM-CE) that allows the prediction of conducted emission generated by an IC at a printed circuit board (PCB) level. However, the EMC levels may change after a certain period of operation due to the aging of components. On the other hand, no existing model or tool can predict the long-term EMC levels. This paper presents a new methodology for modeling of ICs in order to construct an EMC model, which takes into account the aging based on a new reliability model called MultiphySics mulTistressOrs predictive Reliability Model (M-STORM).