Circuit Blocks Research Articles

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

A Proposed On-Die Oscilloscope for Monitoring of Power Noise Waveform Inside IC Due to Transient Stress Events

An on-die oscilloscope circuit is proposed to monitor the power noise waveforms inside IC due to the transient stress events for a more complete analysis of the effects of the transient stress events on the electronic systems. When the transient stress event occurs, the induced noise voltage waveform in the power supply is sampled and converted to digital data in real time. A trigger signal created by the event detector circuit is used to hold the digital data. The stored digital data inside the on-die oscilloscope are reconstructed back to the analog noise waveform based on the sampling process. The operation of each circuit block in the on-die oscilloscope is analyzed and validated by simulation and measurement results. The approximate bandwidth of the proposed on-die oscilloscope is extracted from simulation results. The power noise waveforms due to the transmission line pulse events and electrostatic discharge events are measured with an external oscilloscope instrument using cables and directly sampled and reconstructed by the on-die oscilloscope, and these measured and reconstructed analog noise waveforms are compared with each other.

RRAM Compact Modeling Using Physics and Machine Learning Hybridization

Machine learning (ML)-based compact model (CM) provide an alternative way in contrast to physics-based CMs. The advantages of ML CMs include the process-aware capability, expandability, improved behavioral model for a circuit block, and usability for emerging devices. On the other hand, while ML is on the rise, device physics can provide many guidelines in constructing ML CMs. Here, we propose a physics architecture in ML CMs for resistive random access memory (RRAM). The results show that the physics-assisted architecture enables simpler ML models in reference to our previous work of long short-term memory (LSTM)-based RRAM CMs. We found that the discrete state variable with classification is the best model to describe the RRAM set/reset scenario in multistep prediction problems. For the discrete and continuous state variables, the root mean square error (RMSE) on test data is 0.000125 and 0.000119, respectively. In addition, we demonstrate that the transient behavior of set/reset changes can be easily incorporated into the proposed model. Finally, the Verilog-A and HSPICE on a 1T1R cell have also been shown to prove the model feasibility. We suggest that the uniform framework with hybridization in physics and ML should be the most efficient way in future compact device modeling. The code is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/albertlin11/RRAMunif</uri> .

Sequence-dependent model of genes with dual σ factor preference

Escherichia coli uses σ factors to quickly control large gene cohorts during stress conditions. While most of its genes respond to a single σ factor, approximately 5% of them have dual σ factor preference. The most common are those responsive to both σ70, which controls housekeeping genes, and σ38, which activates genes during stationary growth and stresses. Using RNA-seq and flow-cytometry measurements, we show that ‘σ70+38 genes’ are nearly as upregulated in stationary growth as ‘σ38 genes’. Moreover, we find a clear quantitative relationship between their promoter sequence and their response strength to changes in σ38 levels. We then propose and validate a sequence dependent model of σ70+38 genes, with dual sensitivity to σ38 and σ70, that is applicable in the exponential and stationary growth phases, as well in the transient period in between. We further propose a general model, applicable to other stresses and σ factor combinations. Given this, promoters controlling σ70+38 genes (and variants) could become important building blocks of synthetic circuits with predictable, sequence-dependent sensitivity to transitions between the exponential and stationary growth phases.

Open Frontiers in Neural Cell Type Investigations; Lessons From Caenorhabditis elegans and Beyond, Toward a Multimodal Integration.

Nervous system cells, the building blocks of circuits, have been studied with ever-progressing resolution, yet neural circuits appear still resistant to schemes of reductionist classification. Due to their sheer numbers, complexity and diversity, their systematic study requires concrete classifications that can serve reduced dimensionality, reproducibility, and information integration. Conventional hierarchical schemes transformed through the history of neuroscience by prioritizing criteria of morphology, (electro)physiological activity, molecular content, and circuit function, influenced by prevailing methodologies of the time. Since the molecular biology revolution and the recent advents in transcriptomics, molecular profiling gains ground toward the classification of neurons and glial cell types. Yet, transcriptomics entails technical challenges and more importantly uncovers unforeseen spatiotemporal heterogeneity, in complex and simpler nervous systems. Cells change states dynamically in space and time, in response to stimuli or throughout their developmental trajectory. Mapping cell type and state heterogeneity uncovers uncharted terrains in neurons and especially in glial cell biology, that remains understudied in many aspects. Examining neurons and glial cells from the perspectives of molecular neuroscience, physiology, development and evolution highlights the advantage of multifaceted classification schemes. Among the amalgam of models contributing to neuroscience research, Caenorhabditis elegans combines nervous system anatomy, lineage, connectivity and molecular content, all mapped at single-cell resolution, and can provide valuable insights for the workflow and challenges of the multimodal integration of cell type features. This review reflects on concepts and practices of neuron and glial cells classification and how research, in C. elegans and beyond, guides nervous system experimentation through integrated multidimensional schemes. It highlights underlying principles, emerging themes, and open frontiers in the study of nervous system development, regulatory logic and evolution. It proposes unified platforms to allow integrated annotation of large-scale datasets, gene-function studies, published or unpublished findings and community feedback. Neuroscience is moving fast toward interdisciplinary, high-throughput approaches for combined mapping of the morphology, physiology, connectivity, molecular function, and the integration of information in multifaceted schemes. A closer look in mapped neural circuits and understudied terrains offers insights for the best implementation of these approaches.

SI Considerations in Flexible Channels on High-Speed Intra-Panel Interface for Large-Size Flat Panel Display Applications

In flat panel display modules with a large-size and high-resolution for TV applications, signaling channels are relatively short on flexible printed circuit (FPC) cable or chip-on-film (COF) package when compared to those of the source PCBs. However, the short distance channels can significantly affect overall signal integrity (SI) performance. Thus, this letter focuses mainly on analysis and design of signal interconnection on FPC cable and COF package in terms of impedance matching and crosstalk. By optimizing the FPC cable design to mitigate crosstalk as well as insertion loss, the opening area of eye diagram was found to be improved more than twice over the previous one. In addition, through adjusting process of on-die capacitance of electro-static discharge (ESD) protection circuitry in the input stage of a high-speed circuit block, the created parasitic inductance of COF package trace was observed to be compensated. This optimization process can improve greatly system performance by widening the input eye opening. Finally, we propose channel design considerations and design guidelines to ensure better SI performance in flexible channels on high-speed intra-panel interface for large-size liquid crystal display (LCD) TV applications.

Разработка функциональной схемы цифроаналоговой системы управления судовым электроприводом

The article considers the direct digital control based on microprocessor technology, which has both the undoubted advantages in implementation and some difficulties, for example, work in real time. When developing the control system, two main problems were taken into account: a compromise in choosing possible equipment and signal processing devices. A function diagram of a digital-analogue control system for a ship electric drive is proposed, with can help to increase the reliability of an electric drive with a variable speed. When an electric drive is monitored and regulated, the current, voltage, drive rotation frequency, and the drive shaft rotation angle are under control. In addition, a functional diagram of an electric drive with frequency control has been developed, in which the signal is converted into analog form using a digital-to-analog converter. The application of a two-phase sinusoidal signal generator and a voltage shaper are proposed for obtaining sinusoidal signals of high stability both in phase displacement and in amplitude, which is important from the point of view of the energy characteristics of the electric drive. Further, the signal is converted to the analog form using a digital-to-analog converter and is used as a reference voltage that generates sinusoidal signals. After choosing the element base it can be concluded that the read-only memory device programming is carried out for each engine separately, in contrast to the rest circuit blocks, which are universal, which creates difficulties for creating a universal control system for a ship electric drive. There has been found the possibility of implementing the control system of the electric drive with frequency current control by using the rational distribution of functions between the microprocessor and digital and analog devices.

Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.

An Impedance Readout IC with Ratio-Based Measurement Techniques for Electrical Impedance Spectroscopy.

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 W for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1, respectively.

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

PurposeFull adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.Design/methodology/approachApproximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.FindingsSimulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.Originality/valueThe proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

Determination of Conducted EM Emissions on DC–AC Power Converters Based on Linear Equivalent Thevenin Block Circuit Models

This article deals with circuit modeling of power systems and more particularly of DC–AC converters used for controlling electric motors. The objective of the model is to be able to assess conducted emission currents at both inputs and outputs for fixed operating power in order to apply appropriate mitigation design rules, such as filtering. First, we propose a linear Thevenin block model of the converter considering it as a five-port linear black box allowing possible interaction between the DC and AC ports. To this extent, the block model is made of an impedance matrix and a Thevenin voltage generators vector. We also propose theoretical relationships allowing the processing of data to generate this model from measurements. Then, we test the linear simplifications on a real DC–AC converter and compare the results to measurements. For this, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter measurements in <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> -mode and currents at the five ports in <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -mode are used for the characterization of the model on a first test setup. The model is then applied and checked by comparing circuit simulated and measured current responses on a modified test setup for which the lengths of the connection cables are modified. Finally, the capability of this block model to extrapolate by calculation the response of other installation configurations is shown considering a filter and its insertion at input/output ports of the converter with much longer cables.

Low‐temperature elevated‐metal metal‐oxide thin‐film transistors and circuit building blocks on a flexible substrate

AbstractA low‐temperature (300°C) thin‐film transistor (TFT) technology based on the elevated‐metal metal‐oxide device architecture has been developed and deployed for realizing basic circuit building blocks on a polyimide (PI) flexible substrate. Both digital and analog circuit blocks have been simulated, fabricated, and characterized. Exhibiting insignificant impact on the performance of the TFTs, a 308‐nm excimer laser was used to lift‐off the PI from its glass‐carrier substrate. Based on a multi‐“threshold voltage” technology allowing both depletion‐ and enhancement‐mode TFTs, alternative area‐saving, ratio‐less building blocks have been designed and simulated. The required tuning of the threshold voltage could be accomplished by selective fluorination, laser annealing, incorporation of multiple semiconducting metal oxides, or deployment of a dual‐gate architecture.

Recent progress in single-molecule transistors: their designs, mechanisms and applications

Single-molecule field-effect transistors (FETs) are the key building blocks of electronic circuits and a unique platform for studying physical mechanisms. Here, the designs, mechanisms and applications of single-molecule FETs are summarized.

Theoretical Study on the Conduction Properties of π-Stacked Single-Molecule Junctions with Stacked Aromaticity

π-stacked single-molecule junctions stacked with π-conjugated molecules have the potential to be used as building blocks for single-molecule scale three-dimensional integrated circuits. In this study, we investigate the relationship between π-stacking distance and conductance in face-to-face π-stacked single-molecule junctions with benzene as the monomer unit using the non-equilibrium Green's function (NEGF), which combines the Hückel molecular orbital (HMO) and density functional theory (DFT) methods. As the π-stack distance between two benzene molecules decreases, the pseudo-para junction, which is insulating, turns conductive. Furthermore, it was found that the cause of this change can be explained by orbital interactions.

Device, Circuit, and System Design for Enabling Giga-Hertz Large-Area Electronics

Recent progress has substantially increased the operating frequency of large-area electronic (LAE) devices. Their integration into circuits has enabled unprecedented system-level capabilities, towards future wireless applications for the Internet of Things (IoT) and 5G/6G. These exploit large dimensions and flexible form-factors. In this work, we focus on giga-Hertz (GHz) zinc-oxide (ZnO) thin-film transistors (TFTs) as a foundational device for enabling GHz LAE circuits and systems. To further understand their operation and limits in the newly possible frequency regime, we incorporate the effects of temperature and of non-quasi-static (NQS) physics into the device models. We then analyze operation including these effects on a fundamental circuit block, the cross-coupled inductor-capacitor (LC) oscillator. It is used in representative LAE systems, namely a 13.56 MHz radio-frequency identification (RFID) reader array for near-field energy transfer, and a 1 GHz phased array for far-field radiation beam steering. Co-design of devices, circuits, and systems is essential for achieving flexible and meter-scale monolithic integrated LAE wireless systems. For these, understanding temperature limitations and the NQS effect is crucial.

Contribution to the Control of the Power Switches of DC-DC Converters with two stages of a Photovoltaic System

The work presented in this article proposes the design and the realization of a PWM controller, which allows the control of the power switches of DC-DC converters of discrete two-stage photovoltaic systems in series. The method employed is based on the use of two drivers by exploiting their functionalities in order to improve and control the two power switches of the discretized photovoltaic system. The proposed technique is validated by experimentation on a photovoltaic system, the upper stage of which can request a floating voltage on the MOSFET drain of up to 30V. the studied PV installation is equipped by a protection circuit block for protect the PV equipments in the event of poor connection or deterioration of elements in system blocks. The simulations and the experiments showed a good functioning of the control unit which ensured: An amplitude of the PWM signals large enough to control the power switches, optimal system operation regardless of load and weather changes and good efficiency, and protection of the installation in the event of malfunction.

Integrated Digital and Analog Circuit Blocks in a Scalable Silicon Carbide CMOS Technology

The wide bandgap of silicon carbide (SiC) has attracted a large interest over the past years in many research fields, such as power electronics, high operation temperature circuits, harsh environmental sensing, and more. To facilitate research on complex integrated SiC circuits, ensure reproducibility, and cut down cost, the availability of a low-voltage SiC technology for integrated circuits is of paramount importance. Here, we report on a scalable and open state-of-the-art SiC CMOS technology that addresses this need. An overview of technology parameters, including MOSFET threshold voltage, subthreshold slope, slope factor, and process transconductance, is reported. Conventional integrated digital and analog circuits, ranging from inverters to a 2-bit analog-to-digital converter, are reported. First yield predictions for both analog and digital circuits show great potential for increasing the amount of integrated devices in future applications.

Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs

Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness.

Messaging Matters: Order of Experience with Messaging at a STEM-Based Museum Exhibit Influences Children’s Engagement with Challenging Tasks

This project examines how the order of messaging during parent–child interactions at a museum exhibit affects children’s engagement with the exhibit. Parents and 4-7-year-olds (N = 64) played at a circuit block exhibit. They were first given blocks with descriptive (e.g., “This is a battery.”) or discovery-prompting (e.g., “There is no wrong way to play.”) messages, and after 90 seconds, given more blocks with the other message type. Children who received discovery-prompting messages second – after being allowed to explore the affordances of the circuit blocks with the descriptive messages – played at the exhibit longer, and participated in more circuit-building challenges on their own. Parents were also sensitive to the order of the messaging; it related to the ways in which they interacted with their children at the exhibit. We conclude by considering how the timing of messages families receive at an exhibit relates to the way they engage with the exhibit. Supplemental data for this article is available online at https://doi.org/10.1080/10645578.2021.2015948 .

Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs.

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.