Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies

Egidio Ragonese

doi:10.3390/app12042103

Abstract

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.

Highlights

The success and pervasiveness of CMOS integrated circuits (ICs) have been mainly due to the continuous technology scaling that has improved transistor performance, even at radio frequency (RF) and mm-wave operations, along with the lower production costs to comply with the mass market requirements
CMOS scaling produces a continuous decrease in the supply voltage, enabling new applications, such as wireless sensor networks (WSNs) and the Internet of Things (IoTs)
A crucial role in RF/mm-wave, low-voltage operation is performed by the reactive components, especially inductive components that can be properly exploited to compensate for the limited voltage headroom

Summary

Introduction

The success and pervasiveness of CMOS integrated circuits (ICs) have been mainly due to the continuous technology scaling that has improved transistor performance, even at RF and mm-wave operations, along with the lower production costs to comply with the mass market requirements. A crucial role in RF/mm-wave, low-voltage operation is performed by the reactive components, especially inductive components (i.e., integrated inductors and transformers) that can be properly exploited to compensate for the limited voltage headroom. Another important contribution is given by the body biasing approach, especially in fully depleted (FD) silicon-on-insulator (SOI) platforms [2], which further improves IC performance at low-voltage supply levels.

Integrated Inductive Components

The Body Biasing Technique

Conclusions