Chip Power Consumption Research Articles

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

A 2-Gb/s point-to-point intrapanel interface for thin-film-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input (`1111100000'). At the RX, a multiphase DLL follows the deskew DLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e-12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 52.4 mW at 2 Gbps with a 0.18- μm complementary metal-oxide-semiconductor process and a 1.8-V supply.

Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism.

A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System

The bulkiness of current electronic nose (E-Nose) systems severely limits their portability. This study designed and fabricated an E-Nose signal-processing chip by using TSMC 0.18-μ m 1P6M complementary metal-oxide semiconductor technology to overcome the need to connect the device to a personal computer, which has traditionally been a major stumbling block in reducing the size of E-Nose systems. The proposed chip is based on a conductive polymer sensor array chip composed of multiwalled carbon nanotubes. The signal-processing chip comprises an interface circuit, an analog-to-digital converter, a memory module, and a microprocessor embedded with a pattern-recognition algorithm. Experimental results have verified the functionality of the proposed system, in which the E-Nose signal-processing chip successfully classified three odors, carbon tetrachloride (CCl4), chloroform (CHCl3), and 2-Butanone (MEK), demonstrating its potential for portable applications. The power consumption of this signal-processing chip was maintained at a very low 2.81 mW using a 1.8-V power supply, making it highly suitable for integration as an electronic nose system-on-chip.

Caisson

Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system's root of trust. We incorporate insights and techniques from designing information-flow secure programming languages to provide a new perspective on designing secure hardware. We describe a new hardware description language, Caisson, that combines domain-specific abstractions common to hardware design with insights from type-based techniques used in secure programming languages. The proper combination of these elements allows for an expressive, provably-secure HDL that operates at a familiar level of abstraction to the target audience of the language, hardware architects. We have implemented a compiler for Caisson that translates designs into Verilog and then synthesizes the designs using existing tools. As an example of Caisson's usefulness we have addressed an open problem in secure hardware by creating the first-ever provably information-flow secure processor with micro-architectural features including pipelining and cache. We synthesize the secure processor and empirically compare it in terms of chip area, power consumption, and clock frequency with both a standard (insecure) commercial processor and also a processor augmented at the gate level to dynamically track information flow. Our processor is competitive with the insecure processor and significantly better than dynamic tracking.

Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18-$\mu\hbox{m}$ CMOS

An 11.75-Gb/s combined decision feedback equalizer (DFE) and clock data recovery circuit in a 0.18-μm CMOS is presented. Various techniques are applied to reduce the chip power consumption. In particular, the feedback path of the DFE is merged with an Alexander phase detector (PD). An analysis on the speed requirements of various blocks in the PD and DFE circuits is performed to determine the optimum power dissipation of each one. It is shown that the chip power consumption is reduced by 31% compared to a conventional design. The chip is capable of equalizing copper cable channels with up to 12-dB loss at the 5.875-GHz Nyquist frequency and consumes 101 mW (not including output buffers) with a 1.8-V supply voltage.

Performance of helical edge milling cutters in planing wood

A new design of a milling cutter with solid helical edge has been developed for improving the performance of cutting wood. Development of the new helical edge milling cutter with its geometries for planing wood has been followed by some research progresses. In this work, a conventional edge milling cutter and helical edge milling cutters were tested in planing spruce wood (Picea abies). The purpose of the research work was to investigate chip flow, power consumption, noise emissions, edge wear, and surface roughness characteristics of the helical edge milling cutters in planing spruce wood. Experimental results showed that the helical edges compared to the conventional edge milling cutter provide better chip flows with nearly axial direction and low flight velocity. Though the extreme helical edges up to 75° inclination angle generate comparable or slightly larger cutting power than the conventional edge, they considerably generate lower sound pressure level of up to 5 dB(A). The helical edge milling cutters are better in wear resistance, suffer less edge fractures, and produce better surface quality of planed wood than the conventional edge milling cutter.

Low-Cost and Robust Control of a DFLL for Multi-Processor System-on-Chip

AbstractFine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement on Globally-Asynchronous Locally-Synchronous (GALS) architectures to ensure low power consumption of the whole chip. Each voltage/frequency island is driven by a voltage and a frequency “actuators”. However, due to process variability that naturally appears with technology scaling, the actuator design must be robust. Moreover, due to area constraints, the control law must be as simple as possible. Last but not least, response time constraints require these controllers to be implemented in hardware. In this paper, the design of a low-cost control law for a full Digital FLL in the context of GALS architecture, in presence of process variability and temperature variations has been proposed. The system has been first modelled, especially, the delay that naturally arises in the sensor has been taken into account. The FLL control has been done with classical control tools. The control problem is original by its hardware implementation that has been done in fixed-point arithmetic. The FLL has been implemented in a GALS chip.

Divide-and-Conquer Way Access for Low Power Mobile Caches

As multi-core design concept is becoming dominant, power consumption of the shared level-2 caches is one of the critical issues along with its performance. This is more significant for mobile processors which are used in battery-powered devices. Designing a cache memory, increasing the cache size or adding more set-associativity is one of the simplest ways to improve the performance for both mobile processor and even general-purpose processors. In mobile processors, however, simple increase of the cache size can significantly affect the chip area and power consumption. Modern integration technologies allow integrating the bigger caches into tiny single-chip multi-core mobile processors, but relevant architectural issues cannot be ignored. These issues will be worse in mobile processors which are integrated in a small form-factor without any cooling fan. In this paper, we propose a novel cache mechanism to reduce power consumption in level-2 cache by using the divide-and-conquer way-accessing technique. This idea is derived from the observation that cache way-hit distribution shows the unbalanced pattern in which primary-way(s) have more way-hits. Based on this way utilizations and activities, we came up with a biased way-access mechanism to get benefits from lower associativity which requires relatively lower power consumption. Considering unbalanced way-hit distribution of the cache, all other ways but primary way(s) can be accessed one step later when the primary way-access has across the miss. By doing that, if way-hits are achieved from the primary-way, power can be saved by turning only primary-way on. However, the penalties from the primary-way misses will not be ignored in access time. Through the careful tradeoff analysis between power-saving and penalty in access time, appropriate cache configurations can be chosen in early design stage.

Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

Abstract. The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency with temperature and process. We present several techniques enabling efficient implementation of this synthesizer, including a switched-resistor loop filter topology that avoids a charge pump and boosts effective resistance to save area, a high gain phase detector that lowers the impact of loop filter noise, and a switched capacitor frequency detector that provides initial frequency acquisition. The entire synthesizer with LC VCO occupies less than 0.36sq. mm in 0.18 m CMOS. Chip power consumption is 3.7 mA at 3.3 V supply (20 MHz output, no load).

Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

SUMMARYThe paper presents an algorithmic approach to a low‐sensitivity design strategy for analog filter pairs based on a gyrator–capacitor prototype circuit. The general structure of the prototype circuit is proposed. It assumed that the generic structure of the prototype circuit can evolve, with the use of additional gyrators, into a circuit with increased redundancy. It is shown that symbolic analysis of the prototype circuit, used to formulate a set of nonlinear algebraic equations, is necessary to achieve a sufficiently high algorithm operation speed. To find a solution to this specific system of nonlinear algebraic equations, different numerical methods are compared. The modified Hooke and Jeeves algorithm is found to be the most effective. The elaborated algorithms and programs are illustrated with the seventh‐order filter pair example. The obtained filter is better than the filter obtained using LC ladder structures with respect to chip area and power consumption, and these improvements are obtained without loss of sensitivity properties. Copyright © 2010 John Wiley &amp; Sons, Ltd.

A Composite Transistor to Suppress Kink Phenomenon in HBTs for Broadband Design

The kink phenomenon in heterojunction bipolar transistors (HBTs) is introduced and mathematically analyzed. A novel composite transistor based on feedback theory is proposed to suppress the kink phenomenon with negligible increase in chip area and power consumption. According to the small-signal analysis, the output impedance of the composite transistor can be represented by an RC series circuit. Thus, the output resistance is a constant value over a wide frequency range. A test die using 2-μm InGaP/GaAs HBT technology from AWSC is fabricated, and a constant real part of S22 is measured from 0.1 to 20 GHz (approaching the HBT's unity-gain frequency). The proposed composite transistor can significantly ease the design for output matching and broadband amplifiers.

Small-Area and Low-Energy $K$-Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding

This paper proposes a new K-best detection method that is efficient in area and energy consumption. To reduce the complexity required in tree expansion and sorting, some children of a candidate are not expanded if they are estimated as inferior ones, and they are not considered in the sorting. In addition, we propose an efficient pipeline scheduling called early forwarding to reduce the overall processing latency and the number of pipeline registers. Employing the relaxed expansion and the early forwarding makes it possible to reduce chip area and power consumption as well as latency. Targeting 4 × 4 16 quadrature amplitude modulation systems, a multiple-input-multiple-output detector integrating four if-best detection units is implemented to validate the proposed method. The four units are operating in an interleaved manner to achieve high throughput. In a 0.18-μm CMOS technology, the entire detector occupies 1.9 mm2 and shows a throughput of 584 Mbits/s. The energy consumed in the proposed detector is 443 pJ per bit at 1.8 V.

Sub-1 V Input Single-Inductor Dual-Output (SIDO) DC–DC Converter With Adaptive Load-Tracking Control (ALTC) for Single-Cell-Powered Systems

In this paper, a sub-1 V input single-inductor dual-output (SIDO) dc-dc converter with an adaptive load-tracking control (ALTC) technology is proposed for single-cell-powered portable devices. Having a minimal number of switches and an optimum current sequence, the proposed ALTC technique adaptively and accurately adjusts storage energy in the form of inductor current according to the actual load condition, without wasting surplus charge and without increasing cross regulation. Moreover, a current-mode ring oscillator with a self-bias current source circuit, in place of the conventional start-up ring oscillator, is proposed to produce a nearly constant system clock for the requirement of sub-1 V start-up procedure. Because the proposed current-mode ring oscillator operates between the start-up process and steady state of the SIDO dc-dc converter, its simplified design efficiently addresses the high switching frequency losses at sub-1 V start-up procedure, reducing chip area and power consumption. The proposed sub-1 V input SIDO dc-dc converter was fabricated via Taiwan Semiconductor Manufacturing Company 0.25 μm 2.5 V/5 V Bipolar-CMOS-DMOS process, and the experimental results show high efficiency of 92% with a good cross regulation smaller than 10 mV.

A Differential Sallen-Key Low-Pass Filter in Amorphous-Silicon Technology

In this paper, the design and implementation of a second-order low-pass filter (LPF) utilizing an amorphous-silicon (a-Si) thin-film-transistor (TFT) process technology is presented. In order to boost the gain of the amplifiers, a positive-feedback technique is developed for the design of a differential operational amplifier (OPAMP) and a differential-difference amplifier (DDA). Based on the Sallen-Key filter structure, DDAs with the proposed gain-enhancement technique are employed for the implementation of the LPF such that the chip area and power consumption can be minimized. Using an 8 μm a-Si technology, the DDA and the LPF are realized for demonstration. Consuming a dc power of 9.5 mW from a 25-V supply, the fabricated LPF exhibits a 3-dB bandwidth of 0.3 Hz. For an input frequency of 0.3 Hz, the measured THD and SFDR are and 23.76 dB, respectively.

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory

Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) nand Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.

Design method for area-efficient and uniform channel DACs

A current-mode driving scheme has significant advantages over other competing driving method, and the scheme does not require the time-consuming threshold voltage sampling process used in recent voltage-mode driving methods. Design considerations for compact and uniform channel DACs in current-mode AMOLED display data drivers are addressed in detail. Furthermore, an 8 bit area-efficient cascaded-dividing DAC and a 9 bit segmented DAC are designed in accordance with the suggested DAC design method. The presented DACs perform outstandingly when compared in terms of a composite DAC performance that comprises chip area, power consumption, sampling frequency, and DAC bit resolution.

A Bidirectional TX/RX Four-Element Phased Array at 60 GHz With RF-IF Conversion Block in 90-nm CMOS Process

A 60-GHz four-element bidirectional phased-array transmitter/receiver (TX/RX) chip with a two bit phase shifter (PS) and IF converter to/from 12 GHz, using a 90-nm CMOS process, is described. The array features 7-dB gain, measured noise figure of 9 dB, IPldB of -19 dBm for RX, and output Psat of +3.5 dBm for TX, drawing 60 mA from a 1.3-V supply. The rms amplitude and phase error of the PS is 0.7 dB and 2° max, respectively, from 57 to 66 GHz. This new architecture, together with the compact layout, decreases chip size by a factor of 2, compared to a separate TX and RX design. The use of passive PSs and combiners reduces the current consumption and minimizes temperature variation. An additional rms error of 0.3° and 0.07 dB was measured from 0°C to 80°C. Total die area is 1.6 × 1 mm2 and 1.6 × 0.65 mm2 with and without an IF converter block, respectively. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this is the first report on a bidirectional 60-GHz array with the lowest reported chip power consumption and size.

An Approach for Adaptive DRAM Temperature and Power Management

High-performance DRAMs are providing increasing memory access bandwidth to processors, which is leading to high power consumption and operating temperature in DRAM chips. In this paper, we propose a customized low-power technique for high-performance DRAM systems to improve DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. We combine the throughput-aware page-hit-aware write buffer (TAP) with low-power-state-based techniques for further power and temperature reduction, namely, TAP-low. Our experiments show that a system with TAP-low could reduce the total DRAM power consumption by up to 68.6% (19.9% on average). The steady-state temperature can be reduced by as much as 7.84°C and 2.55°C on average across eight representative workloads.

A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications

In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the run-time ratio between different IPs. As a result, the minimum power consumption of the processor is only 15 mW, while the overall power consumption is 201 mW. As well as the reduction of power consumption, this work shows impressive performance improvement. The proposed fast modulo operators and adopted division-free algorithm reduces the critical latencies of 3-D display image processing. The proposed fast datapath with parallel architecture increase synthesis rate up to 116 fps which is 17 times faster than a previous work. In addition, reordered operation sequence fixes memory bandwidth regardless of the number of images to be produced. In the 3-D graphics IP and the decoding IP, redundant datapath are merged using an IEEE 754 compliant floating-point vector unit to save both chip area and power consumption, which even reduces the critical latency by 30%.