Abstract
The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism.
Highlights
The dynamic power consumption is represented as P ≒ αCVdd2F, where α is the probability of an output transition, C is the load capacitance, Vdd is the supply voltage, and F is the frequency of output transition
The proposed voltage domain programmable (VDP) design uses multiple voltages in order to decrease power consumption while providing a power-performance tradeoff mechanism. In this VDP technique, by programming the voltage of the logic gate, designers can select different performance levels in the same design. The potential of this VDP design circuit is that the voltage domain can be switched to either a high or low voltage based on the different circuit operational modes
The Dynamic Voltage Frequency Scaling (DVFS) technique [3] is an efficient low power management mechanism shown in Figure 6, which provides for voltage and frequency adjustment that is external to the chip
Summary
The dynamic power consumption is represented as P ≒ αCVdd2F, where α is the probability of an output transition, C is the load capacitance, Vdd is the supply voltage, and F is the frequency of output transition. The proposed VDP design uses multiple voltages in order to decrease power consumption while providing a power-performance tradeoff mechanism In this VDP technique, by programming the voltage of the logic gate, designers can select different performance levels in the same design. The potential of this VDP design circuit is that the voltage domain can be switched to either a high or low voltage based on the different circuit operational modes. The internal power management mechanism switches deigned circuit to low-power mode, allowing fewer gates to use VddH and more gates to use VddL, which increases the utilization balance of these two power supplies. The internal voltage domain reassignment technique can replace the traditional voltage adjustment design using the voltage adaptor, and save on cost
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