Chip Size Research Articles

A Model for Unauthorized Person access in a Particular Area

Abstract: A method of unauthorized person identification in a particular area of an entity includes maintaining a database of identification data specific to the person and condition of entries and time period, providing a unique description for each person enabling access to the person identification data in the database. The automated face recognition system uses a new face-finding and an automated eye- finding approach combined with an intelligent metric. This allows templates to be placed on any size chip or into two-dimensional (2-D) barcodes for selfauthenticating documents, as well as for quick easy transmission over the internet, wireless devices, or Ethernet (i.e., LAN, WAN, etc.). A biometric and identity enrollment camera for collecting personal data includes a slidable main module and at least one modifiable section removable coupled to the main module. The main module includes a processor and one or more biometric sensing devices coupled to the processor. Methods of detecting authorized person identity, differentiating between users of a computerized service, and detecting an unauthorized person. The data management facility may be geographically distributed at a plurality of data management sites and the data storage nodes may exist inside and outside of a particular area of the first person.

Processing methodology for the ITS_LIVE Sentinel-1 ice velocity products

Abstract. The NASA MEaSUREs Inter-mission Time Series of Land Ice Velocity and Elevation (ITS_LIVE) project seeks to accelerate understanding of critical glaciers and ice sheet processes by providing researchers with global, low-latency, comprehensive and state of the art records of surface velocities and elevations as observed from space. Here we describe the image-pair ice velocity product and processing methodology for ESA Sentinel-1 radar data. We demonstrate improvements to the core processing algorithm for dense offset tracking, “autoRIFT”, that provide finer resolution (120 m instead of the previous 240 m used for version 1) and higher accuracy (20 % to 50 % improvement) data products with significantly enhanced computational efficiency (>2 orders of magnitude) when compared to earlier versions and the state of the art “dense ampcor” routine in the JPL ISCE software. In particular, the disparity filter is upgraded for handling finer grid resolution with overlapping search chip sizes, and the oversampling ratio in the subpixel cross-correlation estimation is adaptively determined for Sentinel-1 data by matching the precision of the measured displacement based on the search chip size used. A novel calibration is applied to the data to correct for Sentinel-1A/B subswath and full-swath dependent geolocation biases caused by systematic issues with the instruments. Sentinel-1 C-band images are affected by variations in the total electron content of the ionosphere that results in large velocity errors in the azimuth (along-track) direction. To reduce these effects, slant range (line of sight or LOS) velocities are used and accompanied by LOS parameters that support map coordinate (x/y) velocity inversion from ascending and descending slant range offset measurements, as derived from two image pairs. After the proposed correction of ionosphere errors, the uncertainties in velocities are reduced by 9 %–61 %. We further validate the ITS_LIVE Version 2 Sentinel-1 image-pair products, with 6-year time series composed of thousands of epochs, over three typical test sites covering the globe: the Jakobshavn Isbræ Glacier of Greenland, Pine Island Glacier of the Antarctic, and Malaspina Glacier of Alaska. By comparing with other similar products (PROMICE, FAU, and MEaSUREs Annual Antarctic Ice Velocity Map products), as well as other ITS_LIVE version 2 products from Landsat-8 and Sentinel-2 data, we find an overall variation between products around 100 m yr−1 over fast-flowing glacier outlets, where both mean velocity and variation are on the order of km yr−1, and increases up to 300–500 m yr−1 (3 %–6 %) for the fastest Jakobshavn Isbræ Glacier. The velocity magnitude uncertainty of the ITS_LIVE Sentinel-1 products is calculated to be uniformly distributed around 60 m yr−1 for the three test regions investigated. The described product and methods comprise the MEaSUREs ITS_LIVE Sentinel-1 Image-Pair Glacier and Ice Sheet Surface Velocities: version 2 (DOI: https://doi.org/10.5067/0506KQLS6512, Lei et al., 2022).

A 90‐ to 115‐GHz superheterodyne receiver front‐end for W‐band imaging system in 28‐nm complementary metal‐oxide‐semiconductor

SummaryIn this paper, a broadband superheterodyne receiver (RX) front‐end for millimeter‐wave (mm‐Wave) imaging radar is presented. Realized in 28‐nm CMOS technology, the proposed RX incorporates a wideband low‐noise amplifier (LNA), double‐balanced passive mixers for the dual down‐conversion, a differential power divider, a differential intermediate frequency filters, a current‐mode‐logic divider‐by‐2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four‐stage LNA is devised to realize the high gain and low noise figure (NF) with a common‐gate input stage and three pseudodifferential common‐source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer‐based matching networks with the peak‐staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double‐balanced mixers are implemented with a highly symmetrical layout for broadband down‐conversion. Simulation results show that the mm‐Wave RX front‐end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2‐mW power and occupies a chip size of 1.6 × 0.5 mm2 including all the testing pads. The proposed RX is suitable for W‐band imaging systems.

A Wideband and Low-Power Distributed Cascode Mixer Using Inductive Feedback.

A wideband and low-power distributed cascode mixer is implemented for future mobile communications. The distributed design inspired by the distributed amplifier (DA) enables a mixer to operate in a wide band. In addition, the cascode structure and inductive positive feedback design allow high conversion gain with low-power consumption. The proposed mixer is fabricated using a 130 nm commercial complementary metal-oxide-semiconductor (CMOS) process. It consists of three cascode gain cells and operates with a drain voltage of 1.5 V and a gate voltage of 0.5 to 0.7 V. The fabricated mixer exhibits conversion gain of -2.9 to 3.1 dB at the radio frequencies (RFs) of 4 to 30 GHz and -1.9 to 0.4 dB at RFs of 54 to 66 GHz under the conditions of 8 to 10 dBm of local oscillator (LO) power and 650 MHz of intermediate frequency (IF). The LO-RF isolation is more than 15 dB over the entire measurement band (0.2 to 67 GHz) as the RF and LO signals are applied to different transistors owing to the cascode structure. The total power consumption is only within 12 mW, and the chip size is 0.056 mm2, making it possible to implement a compact mixer. The proposed mixer shows broadband characteristics covering from ultra-wideband (UWB) and the 28 GHz fifth-generation (5G) communication band to the 60 GHz wireless gigabit alliance (WiGig) band.

GaN-based resonant cavity micro-LEDs for AR application

Augmented reality (AR) is emerging as a next-generation interactive display that promotes the interaction between users, digital content, and the real world. Although micro-LED is regarded as the most promising light engine candidate for AR, its inherent Lambertian radiation characteristics and relatively broader emission spectrum result in low optical coupling efficiency and diffraction dispersion-related “rainbow” phenomenon when combined with a waveguide combiner. Here, we numerically and experimentally demonstrate resonant cavity (RC) micro-LEDs by incorporating SiO2/TiO2 distributed Bragg reflectors with chip sizes of 60, 100, and 150 μm. The device has a divergence angle of 78.7° and a narrow spectrum width of 6.8 nm, which is significantly lower than that of the controlled micro-LEDs. The reported GaN-based RC micro-LEDs have the potential to be used in the display panel for AR applications in a variety of scenarios, including AR glasses, and head up display for cars and airplanes.

A wideband accurate compact 6‐bit phase shifter in 0.15‐μm GaAs technology

AbstractA Ku wideband accurate compact 6‐bit digital phase shifter is designed in this letter using three different switched phase shift structures: the switched L/C structure, T‐type structure, and high‐pass/low‐pass network. To improve the bandwidth and the gain flatness, an improved switched L/C structure is used and the systematic cascade sequence of the phase shifter is optimized. The improved switched L/C structure solves the problem that conventional L/C networks are hypersensitive to the coupling capacitance at high‐frequency input. As a result, the improved L/C structure can achieve wideband and better s‐parameters. The proposed 6‐bit switched phase shifter is implemented in 0.15‐μm GaAs pHEMT process. The measured root‐mean‐square (rms) phase error is less than 2.8° at 12–18 GHz, and the average insertion loss (IL) is 6.5–6.9 dB. The chip size of the proposed 6‐bit digital phase shifter is 3.1 × 1 mm2, including all RF and dc pads, which is very suitable for radar systems.

Investigation of the Effect of ITO Size and Mesa Shape on the Optoelectronic Properties of GaN-Based Micro LEDs

In this paper, in order to explore the influence of indium tin oxide (ITO) size and mesa shape on the performance of GaN-based micro light emitting diodes (Micro LEDs) on sapphire substrates, Micro LEDs of different sizes with ITO area smaller than or equal to the light-emitting area were designed and fabricated. The experiment results show that when the ITO area of the Micro LED is equal to the area of the light-emitting area, its optoelectronic performance is significantly better than that of the Micro LEDs whose ITO area is smaller than the area of the light-emitting area. When the light-emitting area size is 40 μm, the wall-plug efficiency (WPE) of the two structures of Micro LEDs can differ by more than 50%. Based on above experiment results, this paper designed and fabricated Micro LEDs with different sizes of square and circular mesa with the same ITO area as the light-emitting area. The experimental results show that the WPE of the circular mesa Micro LED is slightly higher than that of the square mesa Micro LED at low current density. However, as the current density and chip size increase, the performance of the Micro LED with a square mesa is better.

Degradation in Efficiency of InGaN/GaN Multiquantum Well Solar Cells With Rising Temperature

In this article, the authors theoretically and experimentally investigate the mechanism of degradation of InGaN/GaN multi-quantum well (MQW) solar cells. InGaN/GaN MQW solar cells with chips of size <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times1$ </tex-math></inline-formula> mm2 were fabricated and characterized within a range of temperature of 50 °C–250 °C to determine the effects of dislocations on their efficiency. The internal intensity of X-ray diffractions was used to construct a 2-D physical model of the density of edge dislocations in the InGaN/GaN MQW that was then simulated in Silvaco. The results show that the relative error in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\eta $ </tex-math></inline-formula> between the simulation and the experiment was less than 5% over the examined range of temperature. This shows that an intensified number of nonradiative recombinations owing to high temperature contribute to edge dislocations that eventually degrade the performance of photoelectric devices. The work here provides a theoretical and experimental basis for the growth of high-quality InGaN materials to fabricate highly efficient solar cells.

A 208–233-GHz Frequency Doubler With 1.1% Power-Added Efficiency in 28-nm CMOS

This letter presents a fully integrated frequency doubler in the TSMC 28-nm CMOS technology. MOS transistor capacitor neutralization is introduced in the differential driving amplifier, which shows better robustness than MOM capacitor neutralization under PVT variations. Besides, a stacked transformer-based balun is designed to achieve good balance performance. The effect of dummy metal on the performance of the proposed balun is also discussed. The measured results show that the 3-dB bandwidth is 25 GHz (208–233 GHz) and the peak power-added efficiency is 1.1% with a dc power consumption of 26.4 mW at 222 GHz. The peak conversion gain is −7.2 dB and the variation in conversion gain is less than 1 dB within −7- to 1-dBm input power range. Moreover, the chip size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$492\times 412\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> , including GSG and DC pads.

28-GHz Dual-Mode Phase-Invariant Variable-Gain Amplifier With Phase Compensators

A 28 GHz dual-mode phase-invariant wide-dynamic-range variable-gain amplifier (VGA) with adaptive phase compensators is presented for use as a gain control element in a beamforming IC, which must have a small chip size and low power consumption. It consists of a single-stage differential amplifier with main and auxiliary signal paths, where the auxiliary paths are introduced to achieve most-significant-bit (MSB) gain control. The wide-gain dynamic range is also covered through a least-significant-bit (LSB) gain-control scheme, which is implemented with bias control of common gate (CG) transistors in the main signal paths. In addition, the phase variations due to the gain controls are drastically reduced by introducing phase compensators for both gain controls. The proposed VGA shows a gain dynamic range of 24 dB, maximum gain of 13 dB and root-mean-square (RMS) phase error of 2.77 degrees at 28 GHz. The maximum DC power consumption is 24 mW at the maximum gain, the minimum is 4 mW at the minimum gain, and the chip size is 0.066 mm2.

An 11–40-GHz High-Power Switch With Miniaturized High-Order Topology Using 100-nm GaN-on-Si HEMTs

This article proposes an ultrawideband switch with miniaturized high-order topology. A 100-nm gate-length GaN-on-Si process is used for high-power capability, and the modeling of the GaN high-electron-mobility transistors (HEMTs) is given to analyze its parasitic values. For wideband or high isolation, the high-order switch is one solution, whose die area is naturally large. To address this issue, a miniaturized coupled-resonator switch topology was proposed using inverter transformation, where two parallel LC tanks and four inverters are replaced by two series LC tanks. Furthermore, a miniaturized coupling structure is introduced using a common inductor to replace three individual ones, contributing to an 86% size reduction. For demonstration, one 11–40.5-GHz single-pole single-throw (SPST) switch with four transmission poles (TPs) has been designed and fabricated. A small chip size of 0.32 mm2, low ON-state minimum insertion loss (IL) of 0.55 dB, and a high-power capability of 1.3 W are achieved.

Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication

We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the dicing process on the warpage reduction and the thermal stress of bonded wafer are investigated by varying the dicing pitch from a one pitch as chip size to a quarter pitch. When the dicing pitch decreases to a quarter pitch, the bonded wafer warpage is observed to decrease by 27.8%. A full wafer model is established with the representative volume element (RVE) method in simulation and validated by good agreement with the measured wafer warpage data. The radial stress distribution of bonded wafer indicates tensile stress for the dynamic random access memory (DRAM) layers and compressive stress for the DRAM/Si substrate interface of top and bottom wafers due to the shrinkage of the DRAM layers under the temperature decrease from its high fabrication temperature to the room temperature. The radial stress distribution after the dicing process with different pitches indicates a similar stress level after one-pitch dicing and half-pitch dicing. When the dicing pitch decreases to a quarter value, the compressive stress decreases, correspondingly resulting in a warpage reduction. The stress released by interrupting the continuity of the wafer with a small dicing pitch is revealed to be the origin of wafer warpage reduction. This study provides a guideline of dicing street pitch for warpage reduction and is useful for optimizing the device layout design.

Investigation on minimum uncut chip thickness and size effect in micro milling of glow discharge polymer (GDP)

Glow discharge polymer (GDP) is used as the ablator material in inertial confinement fusion (ICF) applications. Its machining surface quality and geometric accuracy directly affect its high energy performance. Minimum uncut chip thickness (MUCT) and size effect are the keys to obtain higher surface quality during micro cutting. In this work, a hybrid analytical model of MUCT using cutting forces and effective rake angle based on minimum energy method (Model A), and micro milling experiment are applied to determine the MUCT of GDP. Furthermore, a specific cutting energy-based model (Model B), considering the mechanical properties, strain evolution, and tool geometry, is established to verify model A. Additionally, the material removal mechanism and size effect are also studied. It is found that the MUCT value of GDP determined by model A is between 0.268 and 0.532 μm, and the normalized MUCT value is between 0.148 and 0.295. These results are verified by the specific cutting energy obtained from model B. It is also proved that model B could preliminarily evaluate the MUCT value of GDP without conducting milling experiment. Moreover, below the MUCT threshold, the severe size effect and ploughing effect cause nonlinearly increase of specific cutting energy, and the random variation of cutting force and surface roughness. When the ratio of feed per tooth to cutting edge radius is larger than 0.61, the size effect could be ignored since the cutting mode is shearing.

Mapping Ice Flow Velocity of Tidewater Glaciers in Hornsund Fiord Area with the Use of Autonomous Repeat Image Feature Tracking (2018–2022)

Dynamic climate changes are particularly apparent in polar regions. Glaciers are retreatng towards the land at a very fast pace. This study demonstrates the application of the feature tracking method in the analysis of ice flow velocity in the region of the Hornsund fiord, southern Spitsbergen, in the years 2018–2022. The calculations were based on the Geogrid and autoRIFT environments and on the Sentinel 1 images. The study also employed external data, such as a numerical terrain model and reference velocity values. The input data, e.g., the chip size and the search limit, were prepared accounting for the specific character of the investigated area. The velocities were calculated for nine biggest glaciers which terminated in the fiord. The accuracy of the results was identified by calculating the median absolute deviation (MAD) of the obtained displacement velocity values from the reference value for areas identified as stable. The study also attempted a causal analysis of the influence of weather factors on the dynamics of ice mass displacement. A systematic year-to-year decrease of the velocity was observed for the entire fiord. In the case of several glaciers, changes related to the ablation season (summer) are also clearly visible. The research results are promising and fill a research gap related to the absence of permanent monitoring and analysis of the dynamics of ice flow in polar regions. It is the first complex and precise study of glacier surface velocity changes, performed on the basis of satellite radar images for the entire Hornsund fiord.

Micromilling performance analysis – cold air assisted aluminium machining behaviour observation

The primary goal of this work is to investigate the performance of micro mill tools in terms of tool wear, average surface roughness, and chip size when machining aluminium alloy, as well as to evaluate the effect of cutting fluid application, using a 0.9 mm tungsten carbide (WC) tool with two flutes. This is because it is recognized that one of the essential factors in the micro-cutting process is the micro-cutting tool itself. The tool failure or wear affects the cost, average surface roughness, functionality, and the quality of the finished product greatly. The research is conducted under different cutting conditions with a varying feed rate of 0.001mm/tooth to 0.005mm/tooth and a cutting speed of 3.142m/min to 9.425m/min using a side milling process where the side flank face wear progression of the tool is measured. Then, the average surface roughness and chip size data are collected using a 3D laser measurement microscope. Based on the results, there is a similar tool wear trend in the micro-cutting process with the conventional methods. The results show that the use of cutting fluid has a significant impact on the quality of machined parts, both in terms of burr formation and machined surface quality. The relative size of the burrs formed is much larger than in macro machining operations, depending on the cutting conditions. Tool life and surface finish are impacted by built-up edges on cutting tools. The premature tool failure of the dry condition micro-cutting process is often focused on the entrance of the work-piece. Other than that, it is found that there are some instances where the average surface rough-ness decreases abruptly when it is reaching the fracture zone which is caused by the geometrical effect from the worn edge of the tool. This could be applied in the future design of the micro tool suitable for high-speed machining in dry conditions. It is also concluded that an appropriate selection of machining conditions has the potential to reduce tool wear rate and encourages longer tool life.

Laser diode-pumped compact hybrid lithium niobate microring laser.

We demonstrate a compact hybrid lithium niobate microring laser by butt coupling a commercial 980-nm pump laser diode chip with a high-quality Er3+-doped lithium niobate microring chip. Single-mode lasing emission at 1531-nm wavelength from the Er3+-doped lithium niobate microring can be observed with the integrated 980-nm laser pumping. The compact hybrid lithium niobate microring laser occupies the chip size of 3 mm × 4 mm × 0.5 mm. The threshold pumping laser power is 6 mW and the threshold current is 0.5 A (operating voltage 1.64 V) at atmospheric temperature. The spectrum featuring single-mode lasing with small linewidth of 0.05 nm is observed. This work explores a robust hybrid lithium niobate microring laser source which has potential applications in coherent optical communication and precision metrology.

Comparative Analysis of CMOS based Full Adders by Simulation in DSCH and Microwind

The decrease of surface area is a critical concern for any type of digital circuit. For example, the VLSI approach is used to lower the chip's size, which increases both the device's density and its performance. When it comes to digital circuits, a full adder circuit is a crucial part of any arithmetic processor. A computer, or any other type of computer, will have this component. Most arithmetic operations performed as of now are 64 bits. As a result, we need a sizable amount of room to complete this procedure. We can also take use of these advantages even if we increase the number of bits that need to be processed in parallel. This research attempts to demonstrate how a 4-bit CMOS-based full adder circuit is designed and simulated using Microwind and DSCH at various technology levels. It is then compared to determine if the transistor size may help achieve those benefits. Afterwards. A four-bit binary addition is the goal of the circuit that was built. A 4-bit full adder may be built using a totally automated CMOS design process. The concept and layout of a 4-bit full adder are developed in the initial CMOS design. With nodes of 90, 65 and 45 nm, the designs are produced and modelled utilizing technology. Digital integrated circuits with smaller nodes perform better when compared to those with larger ones, according to simulation findings and distinct outputs.

Warpage characterization of a large size fan-out panel subjected to inhomogeneous heating by a digital fringe projection system

Warpage is an essential issue of fan-out wafer/panel level packaging. Increasing size of wafers/panels poses new challenges to the warpage characterization system. In this work, a warpage measurement system based on digital fringe projection method is reported. It can cover 600 mm × 600 mm area with 4 × 4 camera array. Benchmark tests were carried out to evaluate the measurement error, which was found to be 0.053 %. The warpage evolution of a 515 mm × 510 mm panel with inhomogeneous heating was then studied by heating from room temperature to 90 °C. It was found that the warpage evolution of a large size panel can be very complex. Based on finite element modeling results, this can be attributed to temperature gradient, and several other factors, including mismatch of coefficient of thermal expansion, gravity, initial stress state and original layout design of the panel (such as size and count of chips, RDL design and chip position).

Rapid calculation method to evaluate thermal management of LED systems based on an improved multi-layer model

An improved laminated structure model of LED systems is proposed. Besides the light-emitting diode (LED) chip, printed circuit board (PCB) substrate, heat sink, etc, additional interface layers are applied to model the non-ideal surface of thermal interface materials (TIMs). And a rapid calculation method is developed for temperature-related calculations. Through comparisons, the method is proved to be valid, and the execution time can be greatly reduced. It is found that the air gap at the TIM surface does hinder heat conduction but the effect is not obvious. The influence of LED chips on system thermal management is comprehensively analyzed. For a single LED chip, the junction temperature shows a linear relationship with its thermal resistance and heat power. The chip size, as well as the aspect ratio between the chip and the PCB substrate, has great effects on the junction temperature. For a multi-chip array, the impact of the chip quantity is suggested to be considered combined with the chip layout. The mutual thermal interaction among LED chips is of most concern, which will become more serious with an increasing number of chips. The work provides a rapid and flexible evaluation method for thermal management of LED systems.

Micro LED Display Pixel Circuit Using Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistor

Micro LED (μ-LED) refers to a micro-light emitting diode with a chip size of 5 to 100 μm. Since micro-LED displays use individual LED chips as a light source of the pixel, they do not need backlight and color filters, which are suitable for implementing flexible displays. In addition, micro-led displays have many advantages over OLED displays, such as excellent color gamut, power consumption, lifetime, and response time. With these advantages, micro-LED displays are attracting attention as next-generation displays, and accordingly, interest in micro-LED driving technology is increasing. While existing OLED displays express grayscale by controlling the amount of current flowing through the light-emitting device, micro-LED can have a problem of color change depending on the grayscale because the light-emitting wavelength shifts when the amount of current changes. Therefore, in order to express a certain color, it is necessary to express the grayscale by adjusting the emission time at the same current density. That is, it is more suitable to use the PWM(pulse width modulation) for each pixel than to use the PAM(pulse amplitude modulation) for the grayscale representation of the OLED display. Therefore, unlike OLED, the micro-LED display requires a new pixel circuit because it must use a PWM driving. In addition, unlike LCDs, micro-led displays are sensitive to changes in electrical characteristics of TFTs depending on the location of each pixel or external stress. Thus, threshold voltage compensation is essential because changes and degradation of the characteristics of the thin film transistor backplane, such as threshold voltage shift, cause non uniform brighteness. Therefore, we propose a PWM compensation pixel circuit based on a-IGZO TFT that can be fabricated on a flexible substrate and has a lower process cost than LTPS and greater mobility than a-Si TFT.The operation of proposed pixel is divided into (1) reset 1, (2) PWM data compensation, (3) reset 2, (4) CCG (constant current generation)compensation, and (5) emission. The circuit is divided into a CCG unit that generates a constant current and a PWM unit that adjusts emission time by a ramping signal. Figure 1 (a) shows the output current simulation result according to PWM data voltage variation. When the PWM data voltages vary from -1 to ~ - 5V, the currents were constant at 70.9 μA, and the smaller the PWM data voltage, the longer the emission time was. In addition, Figure 1 (b) shows the effect of the threshold voltage compensation. The current and emission time are constant for various threshold voltages such as 1, 2, and 3 V. Figure 1