Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication

Abstract

We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the dicing process on the warpage reduction and the thermal stress of bonded wafer are investigated by varying the dicing pitch from a one pitch as chip size to a quarter pitch. When the dicing pitch decreases to a quarter pitch, the bonded wafer warpage is observed to decrease by 27.8%. A full wafer model is established with the representative volume element (RVE) method in simulation and validated by good agreement with the measured wafer warpage data. The radial stress distribution of bonded wafer indicates tensile stress for the dynamic random access memory (DRAM) layers and compressive stress for the DRAM/Si substrate interface of top and bottom wafers due to the shrinkage of the DRAM layers under the temperature decrease from its high fabrication temperature to the room temperature. The radial stress distribution after the dicing process with different pitches indicates a similar stress level after one-pitch dicing and half-pitch dicing. When the dicing pitch decreases to a quarter value, the compressive stress decreases, correspondingly resulting in a warpage reduction. The stress released by interrupting the continuity of the wafer with a small dicing pitch is revealed to be the origin of wafer warpage reduction. This study provides a guideline of dicing street pitch for warpage reduction and is useful for optimizing the device layout design.