Comparative Analysis of CMOS based Full Adders by Simulation in DSCH and Microwind

Abstract

The decrease of surface area is a critical concern for any type of digital circuit. For example, the VLSI approach is used to lower the chip's size, which increases both the device's density and its performance. When it comes to digital circuits, a full adder circuit is a crucial part of any arithmetic processor. A computer, or any other type of computer, will have this component. Most arithmetic operations performed as of now are 64 bits. As a result, we need a sizable amount of room to complete this procedure. We can also take use of these advantages even if we increase the number of bits that need to be processed in parallel. This research attempts to demonstrate how a 4-bit CMOS-based full adder circuit is designed and simulated using Microwind and DSCH at various technology levels. It is then compared to determine if the transistor size may help achieve those benefits. Afterwards. A four-bit binary addition is the goal of the circuit that was built. A 4-bit full adder may be built using a totally automated CMOS design process. The concept and layout of a 4-bit full adder are developed in the initial CMOS design. With nodes of 90, 65 and 45 nm, the designs are produced and modelled utilizing technology. Digital integrated circuits with smaller nodes perform better when compared to those with larger ones, according to simulation findings and distinct outputs.