A Power Efficient 500MHz Adder

Abstract

This work presents novel 1-bit full adder and 1-bit half adder circuits. The adders primarily utilize pass transistor logic circuit techniques and achieve full voltage levels for the SUM and CARRY outputs. The 1-bit full adder uses only 16 transistors, and the half adder uses only 15 transistors. They are implemented in 2Snm CMOS technology and are able to achieve a fast delay by limiting the critical path to two stages. Under typical conditions and by using a 10fF load capacitance, the 1-bit full adder achieves a power-delay-product, PDP, of 0. 234fJ for the SUM output signal. This is less than half the PDP of the comparable 28-transistor static CMOS 1-bit full adder. Further, the area of the 1-bit full adder is 0.063 $\mu$m2 and was simulated in HSPICE using a 0.9 V supply voltage. Both the 1-bit full adder and 1-bit half adder circuits were used to build an 8-bit Carry Increment Adder, CIA. The 8-bit CIA adder is functional at 500MHz.