Chip Integration Technology Research Articles

The Relationship of immunoglobulin-e and tumor necrosis factor in patients with allergic rhinitis in Babylon province

Abstract Background: Rhinitis is defined as inflammation of the mucous membranes of the nose usually that is accompanied by swelling of the mucosa and a nasal discharge. It is caused by immunoglobulin E (IgE)-mediated reactions to inhaled allergens, smoking and alcohol use, gender, age, overweight, adoption of pets, race, educational achievement, and family history can represent a risk factor for allergic rhinitis (AR). Objectives: To find the effect of electrolytes tumor necrosis factor (TNF)-α and IgE on AR and study the influence of smoking, gender, and obesity (as a risk factor on AR) on the levels of TNF-α and IgE. Materials and Methods: Eighty subjects for this study were enrolled; 40 of those who have AR age ranged between 18 and 50 years. A control group of 40 subjects who appear to be in good health was selected. This study is a case–control study. TNF-alpha concentration and immunoglobulin-E were measured in serum by an enzyme-linked immunosorbent assay (ELISA) technique also The electrolytes concentrations were measured in the serum using an Abbott device with Integrated Chip Technology (ICT) human kit. The electrolytes were also measured in the serum using the Abbott device. Full history was taken from all patients, which include age, residence, smoking, body mass index, and family history of AR. Results: The results reveal a significant difference (P < 0.05) in levels of TNF-α, Ig-E between patients and controls, There was no significant difference between smoker and non- smoker, normal weight and overweight groups in patients and controls groups.

A-078 Accuracy Based Sigma Metrics of Alinity c System as Benchmarked against Roche c701

Abstract Background Assay performance is dependent on the accuracy and precision of a given method. Sigma metric is a well-established tool for objectively assessing such performances. The objective of the study is to evaluate the Alinity c system using a representative set of clinical chemistry assays in an independent central laboratory setting. The analytical performance of the Alinity c assays was compared with the Roche c701 assays using accuracy-based Sigma metrics. Methods Analytical performance of 7 clinical chemistry assays, including sodium, potassium, chloride (Integrated Chip Technology or ICT), Glucose, ALT, AST and creatine kinase (CK), was assessed on the Alinity c System as benchmarked against the Roche c701. The accuracy of the assays was evaluated by testing reference standard materials sourced from Reference Material Institute for Clinical Chemistry Standards (ReCCS)) in Japan or National Institute of Standards and Technology (NIST) in America. The 5-day precision evaluation per CLSI EP15-A3 was performed using the Bio-Rad Lyphochek® Assayed Chemistry Control and two patient sample pools. Linearity was assessed using 9 levels of patient sample pools covering the measuring interval of each assay. Method comparison with Roche c701 assays was performed per CLSI EP9-A3 using 60 patient samples spanning the measurement range. Sigma metrics for each assay were determined relative to the total allowable errors according to the Clinical Laboratory Improvement Amendments (CLIA) specifications. Results Within-lab (total) imprecision for the 7 assays on Alinity c and Roche were all <3.5% CV for both the Bio-Rad Control and patient pools. Alinity c assays showed a better precision performance in all of assays tested. Bias of the 7 assays in reference to the assigned values was all below 7.5% for both platforms. Alinity c exhibited a good correlation with Roche c701 on all 7 assays in the method comparison evaluation. Linearity of the Alinity c assays was validated for the measuring intervals as claimed by the manufacturer. Majority of the assays on both analzyers demonstrated at least 6 sigma performance with Alinity c showing better sigma scores. Conclusion The Alinity c System demonstrated excellent accuracy, precision and linearity in an evaluation of 7 clinical chemistry assays. A majority of the assays demonstrated at least 6 sigma performance, supporting the fitness for clinical use.

The combination of AlN and h‐BN for enhancing the thermal conductivity of thermoplastic polyurethane composites prepared by selective laser sintering

AbstractIn recent years, with the rapid development of 5G communication technology and microelectronic chip integration technology, smart wearable devices with high thermal conductivity are becoming more and more important. The most common method to improve the thermal conductivity of polymers is to introduce fillers with high thermal conductivity for compounding and build a thermal conductivity network inside the system. At present, the main methods of preparing heat‐conducting composites are hot pressing molding, injection molding, and casting molding, but these traditional molding processes are difficult to prepare heat‐conducting composites with complex shapes and structures. Selective laser sintering (SLS) is a new 3D printing technology, which uses the energy provided by laser to melt polymer powder, then sinter layer by layer, stack layer by layer, and finally form printed products. Compared with the traditional molding process, the SLS process has the advantages of a simple manufacturing process, high molding precision, recyclable materials, and wide application, which can realize the design and development of complex structural parts. In this study, TPU composites were successfully prepared by using thermoplastic polyurethane (TPU) polymer as matrix material, AlN and h‐BN as thermally conductive fillers, and SLS technology. When the content of AlN is 20 wt% and the content of h‐BN is 15 wt%, the thermal conductivity of TPU composite is as high as 0.90 W/mK, which is 391% higher than that of pure TPU sintered parts. At this time, the tensile strength of the composite is 17.2 MPa and the elongation at break is 301%, and it still shows good mechanical properties. This work is devoted to proposing a preparation method of flexible and high thermal conductivity composite materials, which can be used to prepare thermal management materials with complex shapes and structures and carriers of smart wearable devices, and has broad application prospects.

Area Efficient Parallel Median Filter Using Approximate Comparator and Faithful Adder

Approximate computing is a novel approach to design area-efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre-sorter and post-merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing window. Approximate compare and swap (CS) blocks that can trade off area at the expense of accuracy are proposed and used in the proposed PMF. Two variants of PMF are realised based on the implementation of approximate CS units in the pre-sorter and post-merge blocks. In PMF-design1, the authors use the exact CS unit in the pre-sorter and approximate CS unit in the post-merge block (hereafter referred to as P-EA) and in PMF-design2, they use approximate CS unit in both pre-sorter and post-merge blocks (hereafter referred to as P-AA). Functionality and accuracy efficacy of the proposed PMFs are verified with the image de-noising application. Synthesis with 90 nm application specific integrated chip technology revealed that to the least, proposed PMFs demonstrate 33.75 and 41.9% area-delay product and power-delay product reductions, respectively, compared to the standard median filter.

Cu–Cu Bonding Using Selective Cobalt Atomic Layer Deposition for 2.5-D/3-D Chip Integration Technologies

The feasibility of using selective thermal cobalt metal (Co) atomic layer deposition (ALD) as high density Cu–Cu interconnect bonding is demonstrated at a low temperature (200 °C) and with minimal surface pretreatment. A Cu/Gap/Cu structure, which emulates 3-D ICs stacking is fabricated. Cobalt ALD showing seamless interconnection between copper (Cu) pads with 30- $\mu \text{m}$ pitch is demonstrated with greater than 90% yield through electrical measurements, SEM inspection, EDS, and focused ion beam (FIB) cross section.

Simultaneous sensing of refractive index and temperature based on a three-cavity-coupling photonic crystal sensor.

Healthcare and biosensing have attracted wide attention worldwide, with the development of chip integration technology in recent decades. In terms of compact sensor design with high performance and high accuracy, photonic crystal structures based on Fano resonance offer superior solutions. Here, we design a photonic crystal structure for sensing applications by proposing modeling for a three-cavity-coupling system and derive the transmission expression based on temporal coupled-mode theory (TCMT). The correlations between the structural parameters and the transmission are discussed. Ultimately, the geometry, composed of an air mode cavity, a dielectric mode cavity and a cavity of wide linewidth, is proved to be feasible for simultaneous sensing of refractive index (RI) and temperature (T). For the air mode cavity, the RI and T sensitivities are 523 nm/RIU and 2.5 pm/K, respectively. For the dielectric mode cavity, the RI and T sensitivities are 145 nm/RIU and 60.0 pm/K, respectively. The total footprint of the geometry is only 14 × 2.6 (length × width) µm2. Moreover, the deviation ratios of the proposed sensor are approximately 0.6% and 0.4% for RI and T, respectively. Compared with the researches lately published, the sensor exhibits compact footprint and high accuracy. Therefore, we believe the proposed sensor will contribute to the future compact lab-on-chip detection system design.

Integrated design of active phased array for low‐altitude detection radar

This article presents an integrated design of active phased array for low-altitude detection radar. Integrated design is an important method to realise miniaturisation and low cost. The multifunctional integrated chip technology is used to design the tile-type transmit/receive module. The whole array is divided into subarrays for modularisation. In addition, in order to be integrated with active circuits, a wide-beam and silicon-based antenna is proposed and verified.

Integrated Chip Technologies for Microwave Photonics

Microwave photonic integrated chip technology is an important supporting technology of microwave photonic radar. It can not only realize the multifunction of devices, reduce the volume of microwave photonic radar, but also greatly improve the stability and reliability. This paper introduces the photonic integrated chip technologies based on the commonly used InP, Si, LiNbO3 and their heterogeneous integrations and the optoelectronic integration chip technologies for microwave photonics. Finally, the future development trends is discussed.

In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect technologies available in 3-D-Stacked IC devices do not offer such high densities. Parallel front-end of line wafer processing in combination with wafer-to-wafer bonding and extreme wafer thinning steps in the 3-D System on Chip integration technology schemes enable the increase of 3-D interconnect density. During the extreme wafer thinning process pathfinding and development, different thinning techniques were evaluated to target a final Si thickness specification. In this paper, metrology use cases that were applied in this pathfinding and development phase are demonstrated. Techniques, such as wafer level interferometry, wafer edge inspection and metrology, wafer front side metrospection, and wafer high resolution topography techniques were used to investigate process issues. Metrology data enabled us to determine where the extreme wafer thinning process could be improved. The same techniques were used to validate the improvements and to monitor process stability.

Leveraging on Deep Memory Hierarchies to Minimize Energy Consumption and Data Access Latency on Single-Chip Cloud Computers

Recent advances in chip design and integration technologies have led to the development of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those computers are based on Network-on-Chip (NoC) architectures with deep memory hierarchies. Developing scheduling algorithms to reduce data access latency as well as energy consumption is a major challenge for such architectures. In this paper, we propose a set of algorithms to jointly address the problem of task scheduling and data allocation in a unified approach. Moreover, we present a feasible system model for NoC based multicores considering a three-level memory hierarchy that effectively captures the energy consumed by various elements of system including: processing cores, caches, and NoC subsystem. Simulation results show the superiority of proposed algorithms compared to two state-of-the-art algorithms found in the literature. The experimental results clearly indicate that algorithms performing data and task scheduling in a joint fashion are superior against techniques implementing task and data scheduling separately.

The Package Becomes the System

The benefits of system miniaturization lower-cost, higher electrical performance and better thermal mechanical reliability, than the current approach of discrete component packaging have been discussed at length. Several technologies have been used to address these benefits. SOC, SiP, Fan-In and Fan Out and wafer level packages. Recently there has been much discussion about Fan Out Wafer Level packaging (FOWLP) to integrate the entire system in package. However, actual implementations fall short of a complete system in a package in that only few of the chips and some passives are currently integrated into the FOWLP. But what about the rest of the system? A true system also requires additional components not traditionally considered integrate-able into a package. These include antennas, batteries, thermal structures, RF, Optical, micro-electromechanical systems (MEMs), and micro sensor functions. The current FOWLP package technology as discussed by the media falls short of this type of system integration due to limitations in the number of chips that can be integrated and the lack of sufficient interconnect layers to support these functions in a system. 3D stacking has also been employed to improve the SiP by adding memory components. These implementations are limited to stacking of identical chips with through hole silicon vias (TSV) located remotely from any circuitry. Aurora Semiconductor will introduce a packaging technology where the package becomes the system. We call this technology 4DHSiP™ or 4D Heterogeneous System in package. 4DHSiP™ is a system miniaturization technology in contrast to system on chip (SOC) at the integrated circuit level and system in package stacked ICs and packages (SIP) at the module level. 4DHSiP™ is considered an inclusive system technology in which, SIP, thermal structures and batteries are considered as substantive technologies. 3D stacking is no longer limited by the location of the TSV within the stacked components. Heterogeneous multi-chip sub module layers can be stacked to accommodate additional system components. These layers, when interconnected, form the entire system. By stacking sub module layers, specific component types can be located on the top most layer as needed by specific function (e.g. Bio functions, Optical functions, Antennas). An example of this type of module stacking used to create an optical based system will be shown.4DHSiP™ is a new, emerging system concept where the device, package, and system board are miniaturized into a single system package including all the needed system functions. Such a single system package with multiple heterogeneous ICs provides all the system functions by co-design and fabrication of digital, radiofrequency (RF), optical, micro-electromechanical systems (MEMS) in either the IC or the system package. 4DHSiP™ combines the best on chip and off chip integration technologies to develop ultra-miniaturized, high-performance, multifunctional products. A significant benefit of this miniaturization is the elimination of multiple sockets and connectors currently used to connect sub-systems together. This ultra-miniaturization of multiple to mega functions, ultrahigh performance, low cost and high reliability will be the way systems are designed in the future to achieve More than Moore.

Analysis of MEMS Piezoelectric Hydrophone at High Sensitivity for underwater application

Micro-electromechanical systems (MEMS), is a technology that is used to design small integrated devices that combines both electrical (voltage, resistance) and mechanical components (stress, displacement). These devices are assembled using integrated circuit batch processing methods and their size can vary from Micrometers (µm) to Millimeters (mm). MEMS devices have the capability to sense and control the environment. These devices are fabricated using System Integrated chip technology and micro-level segments are manufactured using silicon. To remove the selective parts of silicon i.e. extra silicon parts, Processes such as back etching, high-aspect-ratio micromachining are used to remove selective parts of silicon or to add the extra layers to form the electromechanical components. The study is concerned to design a T- Shape vector Hydrophone using MEMS Technology and to analyses mechanical properties like induced stresses, deformation and to analyses the piezoelectric hydrophone characteristics like frequency response, sensitivity and Voltage to achieve improved sensitivity. MEMS Directional Hydrophone PZT is simulated. Both the structure resembles the fish lateral line and auditory cilia system which converts acoustic pressure into voltage

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

Design Methodology of Network-on-Chip (NoC) for Digital Neural Network

Satisfaction has been found only in research on standard connection method to meet the requirements of SoC design for the past 10 years. But number of core inside SoC may come to exceed 100 because less than 65nm of design method have led to being used according to development of chip integration technology, and expansion of function. And now communication between chip cores entered on a new phase that characteristics of network should be understood by going over simple bus basis. Characteristics of network like this may include receiving socket at the terminal of network to permit independence to cores, and expandability that network may be expanded or reduced at need, as well as standard interface protocol. NoC technology provides on-chip network arranged in a row, by using packet protocol through a series of routers. On the other hand, research on artificial neural network for implementation of human intellectual power with digital technology has continued for a long time, but the research was delayed because of complexity that it should be composed of matrix of numerous processing element (PE). Therefore if digital neural network is designed on the basis of NoC, communication load between PEs, and execution time will be decreased, and design of low power will be possible. And various architecture of digital neural network can be implemented because recomposition and modification of digital neural network is easy.

A comprehensive integration infrastructure for embedded system design

A System-on-a-Chip (SoC) is the most successful example of how the evolution of the chip integration technology allows the manufacture of complex embedded systems. However, the bulk of the design effort, to efficiently combine the HW and SW components in a SoC, still resides in the HW/SW interfacing architecture. A good HW/SW integration strategy has a positive impact either in performance, efficiency, development times, productivity or reutilization of platforms for future designs.In this paper, we present an object-oriented approach to cope with the HW/SW integration problem in SoCs. The Object-Oriented Communication Engine (OOCE) is a system-level middleware particularly designed for SoCs which provides a high-level and homogeneous view of the system components based on the Distributed Object paradigm. Communication between components is abstracted by means of a HW implementation of the Remote Method Invocation semantics and all the SW and HW adapters are automatically generated from functional descriptions of the components interface. The resulting communication infrastructure simplifies the integration effort required and makes the embedded software more resilient to changes in the HW platform.To prove the viability and efficiency of our proposal a prototype implementation on the Xilinx ML505 evaluation platform has been performed.

Wafer-Level Parylene Packaging With Integrated RF Electronics for Wireless Retinal Prostheses

This paper presents an embedded chip integration technology that incorporates silicon housings and flexible Parylene-based microelectromechanical systems (MEMS) devices. Accelerated-lifetime soak testing is performed in saline at elevated temperatures to study the packaging performance of Parylene C thin films. Experimental results show that the silicon chip under test is well protected by Parylene, and the lifetime of Parylene-coated metal at body temperature (37°C) is more than 60 years, indicating that Parylene C is an excellent structural and packaging material for biomedical applications. To demonstrate the proposed packaging technology, a flexible MEMS radio-frequency (RF) coil has been integrated with an RF identification (RFID) circuit die. The coil has an inductance of 16 μH with two layers of metal completely encapsulated in Parylene C, which is microfabricated using a Parylene-metal-Parylene thin-film technology. The chip is a commercially available read-only RFID chip with a typical operating frequency of 125 kHz. The functionality of the embedded chip has been tested using an RFID reader module in both air and saline, demonstrating successful power and data transmission through the MEMS coil.

How to make chip integration technology suitable for high volume production

PurposeThis paper aims to present an overview of existing component embedding methods and to show the differences of the new embedding method called SEAG iBoard.Design/methodology/approachIn most existing embedding technologies bare dies are embedded and contacted to the PCB by through hole plating technologies of the PCB industry. The new method uses a preassembled interposer for embedding which leads to rewiring of the chip contacts to larger pads on the interposer. In a next step passive components will be added to the active die on the same interposer.FindingsThe use of an interposer for embedding leads to a better compatibility of chip processes and PCB processing. Unlike other approaches, the PCB processes can be kept more or less the same as for standard production. Therefore, this new method is suitable for volume applications. The method also shows competitive advantages. Up to now the reliability tests showed a very high reliability of interconnects between the Si‐chip and PCB. Up to 5,000 TCT between −40° and 140°C could be demonstrated. These tests have been performed with daisy chain test chips.Research limitations/implicationsThe qualification results have to be confirmed with functional chips. The principle of this technology is to receive larger interconnection pads by the use of an interposer. Therefore, this technology might have limitations, where lengths of signal paths play the dominant role.Originality/valueThe paper shows how problems in the existing embedding technologies can be overcome. It shows that the preconditions for high reliability at reasonable cost are given.

Yield-improving test and routing circuits for a novel 3-D interconnect technology

Abstract. This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production.

3-D Chip Integration Technology for Microsystems

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