Design Methodology of Network-on-Chip (NoC) for Digital Neural Network

Abstract

Satisfaction has been found only in research on standard connection method to meet the requirements of SoC design for the past 10 years. But number of core inside SoC may come to exceed 100 because less than 65nm of design method have led to being used according to development of chip integration technology, and expansion of function. And now communication between chip cores entered on a new phase that characteristics of network should be understood by going over simple bus basis. Characteristics of network like this may include receiving socket at the terminal of network to permit independence to cores, and expandability that network may be expanded or reduced at need, as well as standard interface protocol. NoC technology provides on-chip network arranged in a row, by using packet protocol through a series of routers. On the other hand, research on artificial neural network for implementation of human intellectual power with digital technology has continued for a long time, but the research was delayed because of complexity that it should be composed of matrix of numerous processing element (PE). Therefore if digital neural network is designed on the basis of NoC, communication load between PEs, and execution time will be decreased, and design of low power will be possible. And various architecture of digital neural network can be implemented because recomposition and modification of digital neural network is easy.