Chip Implementation Research Articles

An Embedded System for a High-Speed Manipulator With Single Time Scale Visual Servoing

This study presents the development of an embedded system for controlling a high-speed robotic manipulator. Three different types of controllers including hardware proportional derivative (PD), software PD, and single time scale visual servoing are considered in this study. Novel field programmable gate array (FPGA) technology was used for implementing the embedded system for faster execution speeds and parallelism. It is comprised of dedicated hardware and software modules for obtaining sensor feedback and control signal (CT) estimation, providing the control signal to the servovalves. A NIOS II virtual soft processor system was configured in the FPGA for implementing functions that are computationally expensive and difficult to implement in hardware. Quadrature decoding, serial peripheral interface (SPI) input and output modules, and control signal estimation in some cases was carried out using the dedicated hardware modules. The experiments show that the proposed controller performed satisfactory control of the end effector position. It performed single time scale visual servoing with control signal updates at 330 Hz to control the end effector trajectory at speeds of up to 0.8 ms−1. The FPGA technology also provided a more compact single chip implementation of the controller.

0.35 μm CMOS–MEMS low-mechanical-noise micro accelerometer

A CMOS–microelectromechanical systems (MEMS) accelerometer chip produced using Taiwan Semiconductor Manufacturing Company 0.35 μm CMOS technology and the Chip Implementation Center micromachining postprocess is proposed in this study. The chip integrates a MEMS gravity sensor and a readout circuit on a silicon substrate. The measured results indicated that the resonant frequency, mechanical noise, static capacitance, sensitivity, and noise floor characteristics were 3.1 kHz, 6.673 μg/√Hz, 120 fF, 2.4 mV/g, and 29.447 μV/√Hz, respectively.

VLSI Implementation of 8051 MCU with Decoupling Capacitor for IC-EMC

In recent years, several new methods for IC-level electromagnetic compatibility (EMC) testing have been introduced. Therefore, a handy vehicle for IC-EMC testing is required to validate the effectiveness of the new IC-EMC testing methods. This paper proposes an 8051 MCU for IC-EMC testing platform with in-system programming (ISP) and decoupling capacitor (decap) functions. In order to reduce the EMI and improve the EMC properties for the 8051 MCU, decoupling capacitors (decaps) are added to the integrated circuit (IC) design flow. Chip-level design and fabrication technology are fundamental and cost-effective solutions to this issue. A cell-based design flow is used for chip implementation; specifically, TSMC 90-nm technology is used to implement the present chip via the National Chip Implementation Center. This study will implement two 8051 MCU chips: one that internally comprises a large number of decaps, and another that comprises no decaps. We also implemented an IC-EMC testing platform composed of a multifunction test board and several off-board probes that were fabricated according to IEC 61967 and IEC 62132 standards. The platform demonstrates a method for using the proposed two 8051 chips in EMC testing, and we reveal the results of its EMC performance. Finally, this study simulates the EMC properties, compares the two 8051 MCU chips, conducts static or dynamic analyses for the chips in a power network, and measures the EMC improvements.

Chip implementation of a new hyperchaotic oscillator

A new four-dimensional hyperchaotic oscillator is proposed. Non-linear dynamic analysis of the hyperchaotic oscillator is presented. Furthermore, an analogue circuit of the hyperchaotic oscillator is implemented on a chip for some relevant engineering applications such as information encryption. The entire chip area occupies 0.69 × 0.84 mm in 0.35 μm CMOS process with power dissipation of 475 mW from a 3.3 V supply voltage.

A CMOS differential receiver dedicated to nuclear magnetic resonance applications

This paper examines the design and implementation of a 21 MHz CMOS differential or so-called dual-path receiver (DPR) dedicated to nuclear magnetic resonance (NMR) spectrometer. This receiver features a CMOS chip incorporated with two mini-Coils and other circuitries. Herein we discuss the design and implementation of the DPR chip as the core part of this new NMR system. The DPR consists of two differential low-noise amplifiers, voltage buffers, phase shifters and variable gain amplifiers in order to accurately cancel the effect of the background NMR signal. We put forward the design and analysis of the DPR chip and thereafter demonstrate and discuss the simulation and experimental results. Based on these results, the front-end receiver achieves a voltage gain of 80 dB at a low input referred noise of 2.7 nV/?Hz. The chip is designed in a 0.13-µm CMOS technology and occupies an area of 1 mm × 2 mm. As per experimental results, this device can be used n the future low-cost NMR technologies.

Design and Analysis of Controller for Vehicle Ignition using FPGA

High death rates are observed after accidents due to non-wearing helmet of driver with two-wheeler. Many studies on statistics data for various parts of world had been carried out which clearly supports this statement. A new approach to address this issue along with the authentication of ownership of vehicle is proposed, which is designed in such way unless an authorized person with RFID tag wears the helmet the vehicle will not be ignited. The paper focuses on the chip design and implementation of hardware system on FPGA for vehicle. The high speed controller is designed Xilinx 14.2 ISE software with the help of VHDL programming language and synthesized on Virtex-5 FPGA. Modelsim 10.1b is used for the function simulation to test the different test cases. The developed system supports the frequency of 781.250 MHz, which is proposed as optimal solution for the intelligent system.

Hybrid shared‐memory and message‐passing multiprocessor system‐on‐chip for UWB MAC layer

Ultra-wideband (UWB) is a well-known radio technology whose media access control (MAC) protocol, WiMedia MAC, has considerable potential to ensure high-speed and high-quality data communication for wireless personal area networks. However, these benefits involve a heavy computational workload, thereby posing a challenge to the conventional very-large-scale integration (VLSI) approach in terms of providing the required performance and power efficiency. Therefore, this study aims to optimise the VLSI implementation of the WiMedia MAC system by proposing a hybrid shared-memory and message-passing multiprocessor system-on-chip (MPSoC) architecture. The proposed solution combines the state-of-the-art MPSoC technology and application-specific instruction-set processor techniques to (i) accelerate the MAC protocol at task level by using parallel processing, (ii) enable the using of custom instructions to optimise the inter-processor communication by using an explicit message passing mechanism, and (iii) ease the implementation process by using a high-level software/hardware co-design methodology. The proposed platform is implemented on both system-level SystemC for architecture exploration and standard-cell technology for future chip implementation. Experimental results show that the proposed hybrid MPSoC architecture achieves 24% performance improvement and 22% power savings over the conventional shared-memory-only one.

The implementation of scale and steel chips waste as a replacement for raw sand in concrete manufacturing

This research study was motivated by the ecological concerns over the disposal of scale and steel chips waste and scarcity of natural sources of raw sand in many countries. This paper reports the findings of an investigation undertaken on concretes made using scale and steel chips waste from the iron and steel industries as a substitute for sand. The percentage of natural sand replaced with scale and steel chips waste varied from 25% to 100% in terms of weight of sand. The concrete was classified according to the concentration of scale and steel chips waste – ScC-25, ScC-50, ScC-75, ScC-100, SchC-25, SchC-50, SchC-75, and SchC-100. The aim of this study is to investigate the compressive strength properties of mixed concrete shields and to compare the thickness of mixed concrete shields with the thickness of ordinary concrete shields (OC-0) to protect against X-ray radiation.For comparison between the thicknesses of mixed concretes and ordinary concrete, we first determined the thickness of OC-0 corresponding to the thickness of concretes with a scale and steel chips waste admixture using lead equivalent (LE). The experimental results were at once rewarding and promising. The results obtained demonstrate a tendency for the thicknesses of mixed concretes to decrease as the mixing ratio of scale and steel chips waste aggregate increases. The data shows that concrete mixed with steel chips waste have better strength than ordinary concrete, while in the case of concrete mixed with scale waste, an addition of over 25% brought about a reduction in compressive strength.

A VLSI implementation of an SM4 algorithm resistant to power analysis

SM4 is a block cipher proposed by the Chinese government. Strengthening the research and extension of SM4 is significant to the development and promotion of Chinese cryptography standards. To date, research relevant to SM4 is rare. Thus, we propose the implementation of an SM4 algorithm resistant to power analysis. Ideally, a secure masking scheme is used for the SM4 cipher, which is particularly suited for implementation in the application specific integrated circuit. Moreover, the mask scheme in our chip implementation process is improved to make SM4 safer. Simulation results confirm that the use of counteractive measures resistant to power analysis is credible.

Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations.

In recent years, deep neural networks (DNN) have demonstrated significant business impact in large scale analysis and classification tasks such as speech recognition, visual object detection, pattern extraction, etc. Training of large DNNs, however, is universally considered as time consuming and computationally intensive task that demands datacenter-scale computational resources recruited for many days. Here we propose a concept of resistive processing unit (RPU) devices that can potentially accelerate DNN training by orders of magnitude while using much less power. The proposed RPU device can store and update the weight values locally thus minimizing data movement during training and allowing to fully exploit the locality and the parallelism of the training algorithm. We evaluate the effect of various RPU device features/non-idealities and system parameters on performance in order to derive the device and system level specifications for implementation of an accelerator chip for DNN training in a realistic CMOS-compatible technology. For large DNNs with about 1 billion weights this massively parallel RPU architecture can achieve acceleration factors of 30, 000 × compared to state-of-the-art microprocessors while providing power efficiency of 84, 000 GigaOps∕s∕W. Problems that currently require days of training on a datacenter-size cluster with thousands of machines can be addressed within hours on a single RPU accelerator. A system consisting of a cluster of RPU accelerators will be able to tackle Big Data problems with trillions of parameters that is impossible to address today like, for example, natural speech recognition and translation between all world languages, real-time analytics on large streams of business and scientific data, integration, and analysis of multimodal sensory data flows from a massive number of IoT (Internet of Things) sensors.

HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications

As are widely used in military and security fields, multiple channels of low-bit-rate vocoders are required to perform on embedded devices efficiently. We propose HAVA, a multicore Application Specific Instruction Set Processor for multichannel low-bit-rate vocoders with real-time performance. To provide both flexibility and efficiency, HAVA integrates two types of processing cores and a shared-memory core on a 2-D-mesh on-chip network. Adopting a single-Instruction Set Architecture heterogeneous multicore architecture, HAVA cuts down the real-time performance requirement of vocoders by over 40% compared with other platforms. By leveraging the on-chip network for intercore communication, HAVA can perform multichannel vocoders with a marginal efficiency loss. The chip implementation of HAVA is finished in a 40-nm CMOS technology and it dissipates 149 mW at 100-MHz operating frequency for four channels of encoders.

NMOS-Based Integrated Modular Bypass for Use in Solar Systems (NIMBUS): Intelligent Bypass for Reducing Partial Shading Power Loss in Solar Panel Applications

NMOS-based Integrated Modular Bypass for Use in Solar systems (NIMBUS) is designed as a replacement for the traditional bypass diode, used in common solar panels. Because of the series connection between the individual solar cells, the power output of a photovoltaic (PV) panel will drop disproportionally under partial shading. Currently, this is solved by dividing the PV panel into substrings, each with a diode bypass placed in parallel. This allows an alternative current path. However, the diodes still have a significant voltage drop (about 350 mV), and due to the fairly large currents in a panel, the diodes are dissipating power that we would rather see at the output of the panel. The NIMBUS chip, being a low-voltage-drop switch, aims to replace these diodes and, thus, reduce that power loss. NIMBUS is a smart bypass: a completely stand-alone system that detects the failing of one or more cells and activates when necessary. It is designed for a 100-mV voltage drop under a 5-A load current. When two or more NIMBUS chips are placed in parallel, an internal synchronization circuit ensures proper operation to provide for larger load currents. This paper will elaborate on the operation, design and implementation of the NIMBUS chip, as well as on the first measurements.

Matrix-Inversion-Free Compressed Sensing With Variable Orthogonal Multi-Matching Pursuit Based on Prior Information for ECG Signals.

Low-complexity compressed sensing (CS) techniques for monitoring electrocardiogram (ECG) signals in wireless body sensor network (WBSN) are presented. The prior probability of ECG sparsity in the wavelet domain is first exploited. Then, variable orthogonal multi-matching pursuit (vOMMP) algorithm that consists of two phases is proposed. In the first phase, orthogonal matching pursuit (OMP) algorithm is adopted to effectively augment the support set with reliable indices and in the second phase, the orthogonal multi-matching pursuit (OMMP) is employed to rescue the missing indices. The reconstruction performance is thus enhanced with the prior information and the vOMMP algorithm. Furthermore, the computation-intensive pseudo-inverse operation is simplified by the matrix-inversion-free (MIF) technique based on QR decomposition. The vOMMP-MIF CS decoder is then implemented in 90 nm CMOS technology. The QR decomposition is accomplished by two systolic arrays working in parallel. The implementation supports three settings for obtaining 40, 44, and 48 coefficients in the sparse vector. From the measurement result, the power consumption is 11.7 mW at 0.9 V and 12 MHz. Compared to prior chip implementations, our design shows good hardware efficiency and is suitable for low-energy applications.

Sorting quantum systems efficiently.

Measuring the state of a quantum system is a fundamental process in quantum mechanics and plays an essential role in quantum information and quantum technologies. One method to measure a quantum observable is to sort the system in different spatial modes according to the measured value, followed by single-particle detectors on each mode. Examples of quantum sorters are polarizing beam-splitters (PBS) – which direct photons according to their polarization – and Stern-Gerlach devices. Here we propose a general scheme to sort a quantum system according to the value of any d-dimensional degree of freedom, such as spin, orbital angular momentum (OAM), wavelength etc. Our scheme is universal, works at the single-particle level and has a theoretical efficiency of 100%. As an application we design an efficient OAM sorter consisting of a single multi-path interferometer which is suitable for a photonic chip implementation.

A New Binary-Halved Clustering Method and ERT Processor for ASSR System

This paper presents an automatic speech–speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI design (here, ASSR system), the hardware cost and time complexity are always the important issues which are improved in this proposed design in two levels: 1) algorithmic and 2) architecture. At the algorithm level, a newly binary-halved clustering (BHC) is proposed to achieve low time complexity and low memory requirement. In addition, at the architecture level, a new ERT core is proposed and implemented based on data dependence and reuse mechanism to reduce the time and hardware cost as well. Finally, the chip implementation is synthesized, placed, and routed using TSMC 90-nm technology library. To verify the performance of the proposed BHC method, a case study is performed based on nine speakers. Moreover, the validation of the ASSR system is examined in two parts: 1) speech recognition and 2) speaker recognition. The results show that the proposed system can achieve 93.38% and 87.56% of recognition rates during speech and speaker recognition, respectively. Furthermore, the proposed ASSR chip includes 396k gate counts, and consumes power in 8.74 mW. Such results demonstrate that the performance of the proposed ASSR system is superior to the conventional systems.

An Embedded Sensor Node Microcontroller with Crypto-Processors.

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed.

Implementation of a hardware security chip for mobile devices

The purpose of this study is to suggest a solution to recently emerging security threats to mobile devices and enable users to use mobile services in a secure manner. To that end, this paper presents the design and implementation method for a hardware security chip required for providing advanced mobile security services. The proposed method could be the fastest and most efficient approach among various approaches. This study implements a Mobile Trusted Module (MTM) chip as a hardware security chip and confirms its commercial potential through interface testing with a smartphone. The implemented MTM chip is based on a smart card IC, and it includes an interface conversion chip that supports the I/O interface with a mobile device. The chip size is 5mm x 5mm, and the chip does not consume more than 10 mA of current. In addition, it provides additional security functions, including the required functions for an MTM chip. Therefore, with the proposed hardware security chip, it is possible to establish a secure service execution environment for mobile devices.

Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems

QR decomposition is a fundamental operation widely used in various signal detection schemes for multiple-input multiple-output (MIMO) systems. In this brief, a high-throughput converted form QR factorization (QRF) is investigated. The proposed two-phase computing scheme starts with a direct form factorization followed by a postprocessing using simple row/column permutations. Using coordinate rotation digital computer (CORDIC) algorithm, a massively parallel array architecture consisting of pipelined and folded CORDIC modules is developed to enhance the throughput. In addition, chaining mode operation is supported, where five successive signal vector updates can be performed the following every factorization. The chip implementation result in TSMC 0.18-μm CMOS process indicates the design, with an equivalent gate count 192100, can operate at 200 MHz and accomplish 25-M complex-valued QRF per second. This suggests a highest 3-Gb/s data rate for signal detections in a 4 × 4 MIMO system. The proposed design also outperforms other designs in two compound performance indices, i.e., data rate normalized with respect to gate count and power consumption, respectively.

A novel pseudo resistor structure for biomedical front-end amplifiers.

This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

Device for Low-Cost Assembly of Chips in RFID Inlays

Security systems employ the RFID method to protect objects and data and to ensure public safety and the safety of commercial activity, e.g. through the control over technological processes. The research activity aimed at improving the level of safety of electronic and technical protection needs to be verified through the manufacture of prototype IDs with RFID inlays.The authors presents an original experimental device enabling the implementation of individual chips in RFID inlays, which were made on a flexible base to which an RFID antenna is attached. The collection of the chip from the dispenser and an unambiguous orientation of the soldered tips in relation to the antenna are provided by a four-axis vacuum manipulator cooperating with a vision system identifying the location of the chip on the manipulator and its final application area. A computer control system enables the operation in two modes, i.e. a semi-automatic mode in which it is possible to manually control the order and the way in which individual tasks are performed, and an automatic mode conducted according to the designed algorithm. The developed device is intended for research on the ways to improve the manufacturing techniques and electronic document protection by means of RFID technologies.