Chip Design Research Articles

Review on low power design of digital integrated circuits

Abstract With the rapid development of science and technology, integrated circuit (IC) plays an increasingly important role in our daily life. Moreover, due to the increasing reduction of chip process size, the IC had greatly improved on its integration and performance. However, because of the improvement of the system complexity and the widely applied to various mobile devices, power consumption becomes an important limitation of the development in chip design. Power consumption not only affects the chip package type and cost, but also causes the increasing of chip temperature, which will directly affect the reliability of chips. On the other hand, high power consumption will also harm the stability of chips. Low power design are becoming more and more imminent, so low-power design are becoming a tendency of designing digital integrated circuits. This paper firstly introduces the importance of nowadays IC research, some background principles and research process of integrated circuits, then analyses the current challenges of designing low-power ICs and also research the power consumption of digital integrated circuits, later explores and analyses the low-power design methods in two different ways. And finally summarize the research status on low-power design circuits with some relevant personal views and the vision to the future are also put forward.

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10-3. The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

Chemical heterogeneity size effects at nanoscale on interface thermal resistance of solid–liquid polymer interface via molecular dynamics simulations

The shrinking size of integrated chips poses thermal management challenges. Understanding the size effect of chemical heterogeneity on solid–liquid interfacial thermal transfer is essential for heterogeneous chip design, yet the underlying mechanisms remain lacking. The present work used the liquid n-alkanes as the thermal interface material between solid platinum substrates. To characterize chemical heterogeneity, periodic solid surface patterns composed of patches with alternating solid–liquid affinities were constructed. By using non-equilibrium molecular dynamics simulations, we investigated the size effect of chemically heterogeneous patterns on interfacial thermal resistance (ITR) at the nanoscale. At larger heterogeneity sizes, i.e., larger patch sizes, most alkane molecules directly in contact weak interaction patches cannot interact with strong interaction patches due to long atomic distances. In the case of alkanes in contact a cold substrate, alkanes in contact weak interaction patches transferred thermal energy to the substrate at a lower rate than those in contact strong interaction patches. The different rates resulted in the higher temperature of alkanes in contact weak interaction patches than those in contact strong interaction patches and, therefore, a larger disparity between temperature jump at the strong interaction areas and that at the weak interaction areas. The non-uniformity of temperature jump distribution increased ITR when compared to the heterogeneous surface system characterized by a smaller patch size with a more uniform temperature distribution in the plane perpendicular to the heat flux direction. In addition, the classical parallel thermal resistance model predicted ITR accurately for the heterogeneous surface systems with small size patches but overestimated overall thermal resistance.

Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability

Rapid progress in CMOS technology since the late 1990s has increased the vulnerability of processors toward faults. Subsequently, the focus of computer architects has shifted toward designing fault-tolerance methods for processor architectures. Concurrently, chip designers have encountered high-order challenges for designing fault-tolerant processor architectures. For processor cores, redundancy-based fault-tolerance methods for fault detection at the core, micro-architectural, thread, and software levels are discussed. Similar applicable redundancy-based fault-tolerance methods for cache memory and hardware accelerators are also presented in the article. Recent trends in fault-tolerant quantum computing and quantum error correction are also discussed. The classification of state-of-the-art techniques presented will help researchers organize their work on established lines.

Ultrastable 3D Heterogeneous Integration via N-Heterocyclic Carbene Self-Assembled Nanolayers.

The commercialization of 3D heterogeneous integration through hybrid bonding has accelerated, and accordingly, Cu-polymer bonding has gained significant attention as a means of overcoming the limitations of conventional Cu-SiO2 hybrid bonding, offering high compatibility with other fabrication processes. Polymers offer robust bonding strength and a low dielectric constant, enabling high-speed signal transmission with high reliability, but suffer from low thermomechanical stability. Thermomechanical stability of polymers was not achieved previously because of thermal degradation and unstable anchoring. To overcome these limitations, wafer-scale Cu-polymer bonding via N-heterocyclic carbene (NHC) nanolayers was presented for 3D heterogeneous integration, affording ultrastable packing density, crystallinity, and thermal properties. NHC nanolayers were deposited on copper electrodes via electrochemical deposition, and wafer-scale 3D heterogeneous integration was achieved by adhesive bonding at 170 °C for 1 min. Ultrastable conductivity and thermomechanical properties were observed by the spatial mapping of conductivity, work function, and force-distance curves. With regard to the characterization of NHC nanolayers, low-temperature bonding, robust corrosion inhibition, enhanced electrical conductivity, back-end-of-line process compatibility, and fabrication process reduction, NHC Cu/polymer bonding provides versatile advances in 3D heterogeneous integration, indicating that NHC Cu/polymer bonding can be utilized as a platform for future 3D vertical chip architectures.

Highly Parallel Droplet Dispensing Approach to Provide Homogeneous and Controllable Droplet Arrays for Diagnostic Test Manufacturing.

We introduce a novel approach for highly parallel droplet dispensing with precise control over the droplet parameters such as droplet volume, droplet velocity, etc. This approach facilitates the fabrication of homogeneous and precise thin layers with uniform coverage on defined small areas (e.g., a specific area of 1 × 1.4 mm2 in microfluidic channels or microwells). The presented approach ensures layer uniformity and high precision in X/Y extent and edge resolution, making it well suited for achieving precise and controlled coating for a variety of applications such as homogeneous coatings for lateral flow tests, ELISA plates, and biosensors for continuous glucose monitoring (CGM) devices. Our approach is based on direct liquid displacement employing a piston that is in direct contact with the liquid and an array of nozzles. Considering a variety of nozzle chip designs (i.e., varying nozzle diameter and pitch), we evaluated a multitude of parameters to derive general design rules for the nozzle chip design. Thus, we achieved a tunable droplet volume from 200 to 800 pL and droplet velocities from 0.5 to 2.5 m/s, applying a nozzle diameter of 50 μm and a nozzle pitch of 165 μm. The presented results showcase the versatility of the approach, offering precise dispensing capabilities.

An energy-efficient 32-bit bit-parallel superconducting SFQ specialized processor

As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.

Physical design for microfluidic biochips considering actual volume management and channel storage

In recent years, microfluidic biochips have been widely applied in various fields of human society. The optimization design of system-architecture based on continuous-flow microfluidic biochips has been widely studied. However, most previous work was based on the traditional chip architecture with dedicated storage, which not only limits the performance of biochips but also increases their manufacturing costs. In order to improve the execution efficiency and reduce the manufacturing cost, a distributed channel-storage architecture can be used to temporarily cache intermediate fluids in idle flow channels. Under this architecture, careful consideration of the volume management of the fluid to be cached is a prerequisite for ensuring the reliability of bioassay results. However, the existing work has not considered the volume management of the fluid to be cached in detail. This may cause the volume of the fluid to not match the capacity of the storage channel, which can contaminate other fluids and lead to incorrect bioassay results or increase the manufacturing cost of biochips due to long storage channels. In this paper, we propose a physical design method for microfluidic biochips that considers the actual volume of fluid while utilizing distributed channel storage. We address this problem by taking a placement and routing co-design strategy throughout the iterative process of the simulated annealing algorithm. Experimental results under multiple benchmarks show that the proposed method can effectively reduce the completion time of bioassays, minimize the flow path length, and decrease the number of intersections.

Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Abstract Convolutional neural networks (CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects (SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm system-on-chip (SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

High‐density implantable neural electrodes and chips for massive neural recordings

AbstractHigh‐density neural recordings with superior spatiotemporal resolution powerfully unveil cellular‐scale neural communication, showing great promise in neural science, translational medicine, and clinical applications. To achieve such, many design and fabrication innovations enhanced the electrode, chip, or both for biocompatibility improvement, electrical performance upgrade, and size miniaturization, offering several thousands of recording sites. However, an enormous gap exists along the trajectory toward billions of recording sites for brain scale resolution, posing many more design challenges. This review tries to find possible insight into mitigating the gap by discussing the latest progress in high‐density electrodes and chips for neural recordings. It emphasizes the design, fabrication, bonding techniques, and in vivo performance optimization of high‐density electrodes. It discusses the promising opportunities for circuit‐level and architecture‐level multi‐channel chip design innovations. We expect that joint effort and close collaboration between high‐density electrodes and chips will pave the way to high‐resolution neural recording tools supporting cutting‐edge neuroscience discoveries and applications.

BAPCP: A comprehensive and user-friendly web tool for identifying biomarkers from protein microarray technologies

Background and Objective:Proteome microarrays are one of the popular high-throughput screening methods for large-scale investigation of protein interactions in cells. These interactions can be measured on protein chips when coupled with fluorescence-labeled probes, helping indicate potential biomarkers or discover drugs. Several computational tools were developed to help analyze the protein chip results. However, existing tools fail to provide a user-friendly interface for biologists and present only one or two data analysis methods suitable for limited experimental designs, restricting the use cases. Methods:In order to facilitate the biomarker examination using protein chips, we implemented a user-friendly and comprehensive web tool called BAPCP (Biomarker Analysis tool for Protein Chip Platforms) in this research to deal with diverse chip data distributions. Results:BAPCP is well integrated with standard chip result files and includes 7 data normalization methods and 7 custom-designed quality control/differential analysis filters for biomarker extraction among experiment groups. Moreover, it can handle cost-efficient chip designs that repeat several blocks/samples within one single slide. Using experiments of the human coronavirus (HCoV) protein microarray and the E. coli proteome chip that helps study the immune response of Kawasaki disease as examples, we demonstrated that BAPCP can accelerate the time-consuming week-long manual biomarker identification process to merely 3 min. Conclusions:The developed BAPCP tool provides substantial analysis support for protein interaction studies and conforms to the necessity of expanding computer usage and exchanging information in bioscience and medicine. The web service of BAPCP is available at https://cosbi.ee.ncku.edu.tw/BAPCP/.

A facile single-cell patterning strategy based on harbor-like microwell microfluidics

Single-cell analysis is an effective method for conducting comprehensive heterogeneity studies ranging from cell phenotype to gene expression. The ability to arrange different cells in a predetermined pattern at single-cell resolution has a wide range of applications in cell-based analysis and plays an important role in facilitating interdisciplinary research by researchers in various fields. Most existing microfluidic microwell chips is a simple and straightforward method, which typically use small-sized microwells to accommodate single cells. However, this method imposes certain limitations on cells of various sizes, and the single-cell capture efficiency is relatively low without the assistance of external forces. Moreover, the microwells limit the spatiotemporal resolution of reagent replacement, as well as cell-to-cell communication. In this study, we propose a new strategy to prepare a single-cell array on a planar microchannel based on microfluidic flip microwells chip platform with large apertures (50 μm), shallow channels (50 μm), and deep microwells (50 μm). The combination of three configuration characteristics contributes to multi-cell trapping and a single-cell array within microwells, while the subsequent chip flipping accomplishes the transfer of the single-cell array to the opposite planar microchannel for cells adherence and growth. Further assisted by protein coating of bovine serum albumin and fibronectin on different layers, the single-cell capture efficiency in microwells is achieved at 92.1% ± 1%, while ultimately 85% ± 3.4% on planar microchannel. To verify the microfluidic flip microwells chip platform, the real-time and heterogeneous study of calcium release and apoptosis behaviours of single cells is carried out. To our knowledge, this is the first time that high-efficiency single-cell acquisition has been accomplished using a circular-well chip design that combines shallow channel, large aperture and deep microwell together. The chip is effective in avoiding the shearing force of high flow rates on cells, and the large apertures better allows cells to sedimentation. Therefore, this strategy owns the advantages of easy preparation and user-friendliness, which is especially valuable for researchers from different fields.

Design of Hybrid Bandpass Filter Chips with High Selectivity and Wideband Using IPD and FBAR Technology

A novel hybrid bandpass filter (BPF) with wideband and high selectivity is proposed in this paper. The hybrid BPF is composed of two film bulk acoustic resonator (FBAR) cells and three lumped component resonators realized by the integrated passive device (IPD) technology. The ABCD matrix to S-parameters matrix method is used to calculate the frequency response of the BPF. Moreover, the expressions of transmission zeros (TZs) have been extracted. In the design process, an iterative design approach is proposed to improve the circuit and layout of the hybrid filter based on the packaged acoustic-electric hybrid simulation effect. Finally, two parts of the filter are packaged based on the flip-chip method, and two prototypes for the BPF are measured. The measured results of two chips with 3 dB fractional bandwidth of 13.7% and 15.8% are designed and fabricated, which verifies the validity of the proposed design principle.

CAIMP: Cross-Architecture IoT Malware Detection and Prediction Based On Static Feature

Abstract IoT malware and cross-platform malware are currently the top threats to information systems. This paper proposes a robust cross-architecture IoT malware detection and prediction model based on machine learning and opcode features using a novel approach. In our method, a feature opcode transformation model between chip architecture platforms is proposed to facilitate the process of building a detection model for cross-architecture malware on IoT devices. The feature transformation model is capable of converting opcodes between different architecture platforms using an unsupervised machine learning approach. In our approach, a machine learning model is used for the detection of cross-platform malware based on the proposed opcode features. Experiments have demonstrated that our method is effective in detecting and predicting cross-platform malware with an accuracy of up to 99.4% and an F1-score of 99.3%. The method is capable of learning on one architecture platform and detecting malware on a different architecture platform. Therefore, the method can be used to develop cross-architecture detection and zero-day malware prediction solutions on IoT devices.

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

Design of IPD-based wideband bandpass filter chips with controllable transmission zeros

ABSTRACT In this brief, two novel wideband bandpass filter (BPF) chips with independently controllable transmission zeros are proposed. BPF I uses bridge T-type highpass and lowpass structures cascaded to achieve wideband filtering. On this basis, BPF II adds three pairs of LC resonant circuits to add additional transmission zeros while retaining the lowpass structures. The analytical methods of odd-even mode and ABCD matrix to S-parameter matrix are used to analyze and calculate two designs. For validation, two prototypes of proposed BPFs in integrated passive device (IPD) have been designed, fabricated, and measured. One prototype operates at 5.3 GHz, providing a 3-dB fractional bandwidth (FBW) of 46.9%, while the other prototype operates at 4.7 GHz, providing a 3-dB FBW of 57.6%. Moreover, the two chips exhibit minimum insertion losses of 1.55 dB and 1.5 dB, respectively, while occupying compact sizes of 2.27 mm × 0.83 mm and 1.7 mm × 0.88 mm.

Flexible zinc-ion hybrid micro-supercapacitors with polymeric current collector for integrated energy storage in wearable devices

The ubiquity of conventional micro-fabrication techniques has encountered impediments in constructing cost-effective micro-devices, thereby constraining their broad deployment. Concurrently, the suboptimal energy density inherent to supercapacitors exacerbates this challenge. This study presents a straightforward assembly methodology for the fabrication of a mechano-electrochemically efficient micro-zinc ion hybrid supercapacitor (M−ZSC), alongside the introduction of an innovative polymeric current collector. The M−ZSC is fabricated through a process involving masked spray deposition of a novel adhesive current collector and the electrode materials, and electroplating of zinc nanosheets onto the anode finger, creating an electrochemically performant and mechanically robust device. The resulting M−ZSC exhibits a notable areal capacitance of 52.2 mF/cm2 and an energy density of 18.5 µWh/cm2 for the normal mass-loading of 3.6 mg/cm2, which is amongst the highest reported values for energy storage. The masked spray deposition/hot pressing technique enabled us to fabricate free-standing thick electrodes with a loading density of up to 56.1 mg/cm2, facilitating the achievement of an ultrahigh areal capacitance of 227 mF/cm2 and an energy density of 80.5 µWh/cm2. Furthermore, the M−ZSC exhibits a robust retention of 95 % capacitance at 1 mA/cm2. Critical to its flexibility, the device is constructed using purely additive deposition methods on flexible substrates and is therefore well-tailored for deployment in flexible electronics and on-chip applications. These micro-devices are well-poised for seamless integration within a singular electronics package or chip architecture.

Fluid Path Detection Model for Lab on a Chip Images Using Deep Learning-Based Segmentation Approach

This paper explores the potential of Lab on a Chip (LOC) technologies in transforming diagnostic, biotechnology, and chemical/mechanical analysis fields. The proposed solution integrates advanced image processing into an automated tool, providing a robust and efficient method for precise data extraction from microfluidic chip images. In this study, we identify the fluid path in each frame, thereby improving the platform for tracking valuable fluid parameters over time, such as the viscosity of biofluids. Different patterns of LOC were developed then captured and related masks were established to create the 150 images dataset.[1]Using the DeepLabv3+ deep learning model on the dataset, this study achieves remarkable validation accuracy of 98.95% and a low loss value of 0.012 for chip analysis path segmentation. The successful integration of DeepLabv3+ and meticulous preprocessing enhances understanding of fluid behavior within microfluidic chips, paving the way for advancements in chip design, diagnostics, and fluid feature-based analyses.

The Edifice of Vasculature-On-Chips: A Focused Review on the Key Elements and Assembly of Angiogenesis Models.

The conception of vascularized organ-on-a-chip models provides researchers with the ability to supply controlled biological and physical cues that simulate the in vivo dynamic microphysiological environment of native blood vessels. The intention of this niche research area is to improve our understanding of the role of the vasculature in health or disease progression in vitro by allowing researchers to monitor angiogenic responses and cell-cell or cell-matrix interactions in real time. This review offers a comprehensive overview of the essential elements, including cells, biomaterials, microenvironmental factors, microfluidic chip design, and standard validation procedures that currently govern angiogenesis-on-a-chip assemblies. In addition, we emphasize the importance of incorporating a microvasculature component into organ-on-chip devices in critical biomedical research areas, such as tissue engineering, drug discovery, and disease modeling. Ultimately, advances in this area of research could provide innovative solutions and a personalized approach to ongoing medical challenges.

Efficient design approaches to CMOS full adder circuits

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.