Chip Corner Research Articles

Modeling of flip-chip underfill delamination and cracking with five input manufacturing variables

The chip corner geometry and the mismatch of the coefficient of thermal expansion cause a local stress concentration in the underfill near the chip corner area. Delamination at the chip-underfill interface and cracks in the underfill often originate from the chip corner and might develop throughout the assembly. This paper presents a modeling approach that allows the estimation of the initial moment of delamination, the growth of delamination and the cracking profiles in flip-chip packages. The reliability model in this work includes five input variables: kerf width, dicing type, laser outrigger presence, sealband material and sealband shape. Thirteen test cells of flip-chip experimental samples were first prepared according to these input variables and were subjected to deep thermal cycling (DTC). C-mode scanning acoustic microscopy (C-SAM), infrared microscopy (IR) and cross-sectioning were used to estimate the underfill failure moments, delamination areas and crack profiles as a reference for subsequent numerical modeling. An artificial neural network (ANN) model was trained to estimate the number of cycles to delamination for cells in the test dataset. The predicted numbers of cycles for all 6 cells in the test dataset were consistent with experimental observations. A finite element model was built to describe the growth of delamination. When the model reached the same delamination area as measured by C-SAM, the difference between the predicted number of cycles and the C-SAM inspection moment were smaller than the inspection interval (250 cycles) for 5 out of 6 cells in validation; the delamination growth model was thus consistent with the experimental observations. The extended finite element method (XFEM) was used to model the underfill cracks without predefined paths. One of the cracks propagated along the diagonal direction, and the other two cracks were along the edges of the die. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5° for the edge cracks. Overall, with five input manufacturing variables, this modeling approach is able to provide reasonable predictions of the number of cycles to chip-underfill delamination initiation, area of delamination and underfill crack paths in flip-chip packages.

Study of underfill corner cracks by the confocal-DIC and phantom-nodes methods

In a flip chip package, due to the sharp square chip corner geometry and the loading from mismatches in the coefficients of thermal expansion between materials in the assembly, a stress concentration in the chip corner area is often thought to greatly impact reliability in thermal cyclic loading. Cracks often originate from this stress concentration, and may lead to the failure of the device when propagating into the chip or electrical connections. In order to better understand the mechanism of underfill cracking and predict the crack path, a method based on laser scanning confocal microscopy and digital image correlation (confocal-DIC) was used to measure the local deformation around a crack from a chip corner. A sample was fabricated by bonding a 6 × 6 × 0.55 mm3 silicon chip to a 20 × 12 × 0.4 mm3 quartz substrate, in a configuration that is similar to a flip-chip package. The SU8-2005 epoxy resin mixed with a mass fraction of 0.1 wt% alumina particle fillers was used as the underfill material for the purpose of measurements. Naturally initiated cracks were observed along the diagonal direction when the sample was subjected to −18/25 °C thermal cycles. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner by a laser, along the 45° diagonal direction, similarly to the naturally initiated cracks. The artificially cracked sample was imaged at 25 °C and 5 °C by a confocal microscope and the strain distribution around the crack was estimated by DIC. The maximum hoop strain and first principal strain were located at the crack front area for both the 160 μm and 640 μm cracks. These data were used to build a numerical model using the extended finite element method (XFEM) with the phantom-nodes approach. When the mesh size was decreased to 16 μm, the hoop strain obtained by simulation at the crack tip was 22.0% and 9.5% lower than that measured by confocal-DIC, for the 160 μm crack and the 640 μm crack, respectively. This difference decreased to 8.2% and 6.3%, respectively, when the distance was from 50 to 175 μm away from the crack tip along the diagonal direction. The distribution of hoop strain was in good agreement with the measured values, when the element size was small enough to capture the strong strain gradient near the crack tip. A propagation model was realized based on the phantom-nodes method. The crack started from the chip corner and evolved into a planar crack along the diagonal direction, which is in good agreement with the experimental observations.

New Failure Mechanism Induced by Current Limit for Superjunction MOSFET Under Single-Pulse UIS Stress

New failure mechanism induced by current limits has been investigated for the superjunction MOSFET (SJ-MOSFET) under single-pulse unclamped inductive switching (UIS) test stress. It is found that the local charge imbalance ( Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> > Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) at the chip corner produces a hotspot during the UIS test. The failure of the device induced by the hotspot depends on the magnitude of the avalanche current. For a low avalanche current, the avalanche current is redistributed from the local charge imbalance region to the charge balance region due to the lattice temperature increasing, resulting in the local heating toward the full-scale heating. However, for a high avalanche current, the negative differential resistance (NDR) effect plays a dominant role in the local charge imbalance region, decreasing the dynamic breakdown voltage (BV) sharply. Therefore, the hotspot is locked at the charge imbalance region; then, the device is destroyed in a short time. Finally, an SJ-MOSFET with more p-type charges at the chip corner is produced to improve the avalanche capability relating to the current limit, also verifying the mechanism analysis.

Using Confocal Microscopy and Digital Image Correlation to Measure Local Strains Around a Chip Corner and a Crack Front

In a flip chip package, the chip corner areas which are embedded in the underfill material are often critical to the damage initiation, since a stress concentration usually exists at these locations. A high level of stress concentration often promotes crack initiation from the chip corner. In order to better understand the local deformation around chip corners and crack tips, a method based on laser scanning confocal microscopy combined with the digital image correlation (confocal-DIC) was developed to measure local strain directly in deformed, transparent objects. A transparent epoxy resin with alumina particle fillers was used in four different types of samples, which were fabricated for the purpose of validation. A non-constrained sample and a thin-layer sample were used to verify the isotropic thermal expansion and the strain gradients with respect to the depth, respectively. Results from both samples were in good agreements with the calculation from the coefficient of thermal expansion (CTE) and FEM simulations. Furthermore, the confocal-DIC technique was applied to measure the strain distribution near the chip corner area of a third sample replicating the geometry of a flip chip package. The measured maximum first principal strain was located at the chip corner, reaching 0.9% at 60 °C, in a good agreement with the simulation results. The strain in front of the crack tip was also evaluated by a three-point bending test in a fourth test sample. The measured maximum strain was 5.8± 0.7%, corresponding to a relative error of only about 5% compared to simulations for a round crack tip configuration. The averaging used in DIC lowers its spatial resolution and makes it difficult to capture higher strain gradients in small regions. However, the confocal-DIC approach appears to be able to provide reasonable results for evaluating the maximum strain and the full field strain distribution in tri-dimensional volumes with geometries, materials and dimensions which are very similar to those of actual flip chip microelectronic packages.

New Thin Adhesive for High Density 2.5D Heterogeneous Device Integration with Cu-Cu Hybrid Bonding

Abstract Heterogeneous integration of logic, memory, and sensor chips on interposers (2.5D) has attracted a lot of attention as a candidate for More-than-Moore technology. For the high performance 2.5D devices, high density integration of chips with narrow spacing and high density interconnections with small pitch bonding electrodes are a key technology. In the current bonding technology, solder micro-bumps (&amp;gt;20 μm in diameter) and non-conductive adhesives have been adopted. There may be some limitations for high density device integration with these technologies because of the protrusion of adhesives around the chips, the thermal sliding at the bonding, and the limit of solder micro-bump minimization. Hybrid bonding with a small Cu electrode (&amp;lt;10 μm in diameter) is a strong candidate for improving advanced device integration technology. Our goal is to develop a new adhesive which gives no protrusion, no thermal sliding, no voids, and high electrical reliability. A spin coating thin adhesive was therefore developed. The new adhesive can be cured at 200 °C. The cured adhesive film has no tackiness and has an optically flat surface. The adhesive film can be temporarily bondable to SiO2 at room temperature. After 200 °C baking, a permanent bonding can be achieved, and there is no degradation of bonding strength and no voids even after 400 °C of baking. For the applicability to the chip-on-wafer process, the adhesive film/Si wafer can be cut into chips by blade dicing without any delamination and without any apparent particles. After bonding the adhesive/Si chip to a bare Si wafer at room temperature, the thermal sliding amount after the thermal compression process (250 °C, 10 min, 1 MPa) was less than 1 μm (under the detection limit) according to optical microscopic measurements. In addition, there was no protrusion of adhesive around the chip corner from SEM. A first trial result for hybrid bonding is also reported.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (∼100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1–0.2 e/Hz from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects

The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures are analyzed. The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures. In addition, the influence of passivation thickness was determined, where a thinner passivation results in a reduced number of failures. In order to visualize the failures, the interconnect stack was exposed after mechanical removal of the package overmold and Si etching. Cracks were present at the corner of the test chip.

A Reliable and Simple Method for Fabricating a Poly(Dimethylsiloxane) Electrospray Ionization Chip with a Corner-Integrated Emitter

Monolithically integrated emitters have been increasingly applied to microfluidic devices that are coupled to mass spectrometers (MS) as electrospray ionization sources (ESI). A new method was developed to fabricate a duplicable structure which integrated the emitter into a poly(dimethylsiloxane) chip corner. Two photoresist layers containing a raised base which guaranteed the precise integration of the electrospray tip emitter and ensured that the cutting out of the tip exerted no influence even during repeated prototyping were used to ease the operation of the process. Highly stable ESI-MS performance was obtained and the results were compared with those of a commercial fused-silica capillary source. Furthermore, chip-to-chip and run-to-run results indicated both reliability and reproducibility during repeated fabrication. These results reveal that the proposed chip can provide an ideal ion source for MS across many applications, especially with the perspective to be widely used in portable MS during on-site analysis.

Evaluation new corner stress relief structure layout for high robust metallization

For a high robust metallization it is necessary to solve different problems related to migration mechanisms and thermo-mechanical stress in the material. Extended operating conditions and challenging assembling processes influence stress behaviour in chip corners. Typically the corner area of the chip is excluded for use. For higher stress load the forbidden area increases. But effort for demanding mission profiles of a product should not cumulative in increasing chip size. Simulation can help to a better understanding of mechanical stress in the chip corner and chip-package interaction.Corner stress relief structures lower the influence of high thermo-mechanical stress. A high functional corner stress relief structure allows a more efficient chip design. In this work of corner stress relief structure is presented and an evaluation structure is shown which allows to prove the effectiveness of the stress relief.

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 µm and by that with high modulus during the bumpless chip-on-wafer (COW) process has been investigated. According to the stress simulation, thermal stresses increase with polymer thickness where the stress value ranges from 100 to 200 MPa for benzocyclobutene (BCB)-based resin. Thermal stresses in the hybrid structure using epoxy-based resin and BCB-based resin were calculated to be less than 100 MPa. Thus, the reduction of the thicknesses of the polymer as well as the Si chip was found to be effective in avoiding crack formation in the COW structure. Moreover, to investigate the crack driving force, the energy release rate (ERR) was calculated. The crack propagates toward the Si chip corner and the result is consistent with the experiment. On the COW structure, a thin Si chip and a low-modulus polymer expand the process window.

Microchip capillary electrophoresis–electrospray ionization–mass spectrometry of intact proteins using uncoated Ormocomp microchips

We present rapid (<5 min) and efficient intact protein analysis by mass spectrometry (MS) using fully microfabricated and monolithically integrated capillary electrophoresis–electrospray ionization (CE–ESI) microchips. The microchips are fabricated fully of commercial inorganic–organic hybrid material, Ormocomp, by UV-embossing and adhesive Ormocomp–Ormocomp bonding (CE microchannels). A sheath-flow ESI interface is monolithically integrated with the UV-embossed separation channels by cutting a rectangular emitter tip in the end with a dicing saw. As a result, electrospray was produced from the corner of chip with good reproducibility between parallel tips (stability within 3.8–9.2% RSD). Thanks to its inherent biocompatibility and stable (negative) surface charge, Ormocomp microchips enable efficient intact protein analysis with up to ∼10 4 theoretical separation plates per meter without any chemical or physical surface modification before analysis. The same microchip setup is also feasible for rapid peptide sequencing and mass fingerprinting and shows excellent migration time repeatability from run to run for both peptides (5.6–5.9% RSD, n = 4) and intact proteins (1.3–7.5% RSD, n = 3). Thus, the Ormocomp microchips provide a versatile new tool for MS-based proteomics. Particularly, the feasibility of the Ormocomp chips for rapid analysis of intact proteins with such a simple setup is a valuable increment to the current technology.

Microscopic stress simulation of non-planar chip technologies

Finite element simulations were used to study the thermo-mechanical stress state at the chip corner in a chip–package system. Accurate geometry of a non-planar chip topology was created by digitizing images obtained with a scanning electron microscope through focused ion beam cuts. Nested sub-modeling approach was utilized in order to simulate the a few microns region of interest, which is very small, compared to 1 cm package size. Available material models were used and unavailable materials were characterized. Thermal loads for the complete set of fabrication process from the wafer initialization to the final qualification phase were considered for this work. Cracks arising in passivation due to thermo-mechanical loads were a concern. Stress simulations on this chip–package system were carried out and compared between planar and non-planar geometries of the same. It was found that the accuracy of stress values largely depend on the precise geometry input for simulation. Preliminary finite element models were optimized to achieve accuracy in the simulation results. The stress measured on test chips with integrated stress cells. The simulation results are in good agreement with these experimental values. This also helped to validate the material models and simulation methodology reported in this paper.

High precision thermal stress study on flip chips by synchrotron polychromatic x-ray microdiffraction

The bending and residual stress of flip chips caused by the mismatch of thermal expansion between the chip and the substrate have been measured by polychromatic microfocused synchrotron x-ray beam. Precise orientation information as a function of position on the chip was obtained from Laue diffraction patterns, so that the bending angle with respect to a reference position at the center of the chip can be calculated at each position. This in turn allows deducing the local curvature of the entire flip chip. Local stress distribution was then mapped by applying a modified Stoney’s stress-strain equation to the measured curvature. Our study shows that thermal stress on the circuits and the solder joints in a flip chip strongly depend on temperature and the distance from the center of the chip, indicating that interconnects at the corner and edge of a flip chip are of reliability concerns.

Improving utilization of reconfigurable resources using two-dimensional compaction

Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance. This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the four-corners compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies: Brebner, G. and Diessel, O. (Proceedings of the 11th international workshop on field programmable gate arrays (FPL), pp. 182---191, 2001); Diesel, O. and ElGindy, H. (Proceedings of the 5th Australasian conference on parallel and real-time systems (PART), pp. 191---200, 1998); Diesel, O., et al. (IEE proceedings on computers and digital techniques, vol. 147, pp. 181---188, 2000). The simulation results show improvement in average task allocation time when using the four-corners compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.

An open question to developers of numerical software

IEEE 754 a standard for binary floating-point arithmetic has revolutionized the portability and reliability of programs that use binary floating-point arithmetic. Floating point is almost universally implemented with special-purpose hardware that tucks into a small corner of the CPU chip and runs in the hundreds of Mflops to Gflops range. Single-stepping through today's floating-point software to debug it often turns out to be futile. The concept of a NaN, standing for "not a number", evolved from an "indefinite" in Seymour Cray's CDC 6600. IEEE 754, by default, requires an untrapped "invalid operation", to signal itself by raising a flag and to deliver a NaN just when any other result, be it finite or infinite, would cause worse confusion. The NaN lets a program retain control unless the program or programmer directs its cancellation upon an invalid operation. Thus, a program conducting a search can return to the realm being searched after an accidental foray beyond a boundary whose existence and location were previously unknown. A sNaN differs from the other quiet NaNs by traooing any attempt to perform arithmetic upon it; then a trap-handler must interpret this sNaN.

Thermomechanical stability of memory package with LOC structure

The present work attempts to determine an appropriate design of double-sided adhesive tape, which plays a significant role in defining the degree of chip surface damage in a plastic LOC (lead-on-chip) package. Various tape designs were tested to determine their effectiveness in preventing thermal stress-related damage on the chip surface during temperature cycling. The experimental results indicate that the thermomechanical stability of the IC pattern is more influenced by whether the LOC tape is employed along the chip edge than by the size of the tape covering area. Moreover, it was found that chip surface damage associated with LOC tape can be caused by normal stress applied to the chip surface vertically as well as by shear stress, which is known to cause damage. The importance of the normal stress component is verified through a 3-dimensional FEM (finite element method) simulation adopted to define the thermal stress distribution in the present LOC package. The numerical calculation shows that when the tape is designed to cover the chip corner, the magnitude of normal stress reveals a maximum value at the edge of the chip.

Thermal analysis of flip chip plastic ball grid array assembly

AbstractSteady‐state thermal performance of the 164‐Lead flip chip plastic ball grid array (FC‐PBGA) under low to moderate convective air cooling conditions is simulated with CFX software. A package with three different substrates is investigated. Package performance is presented in the form of a linear relationship between the normalized junction to ambient thermal parameter (θJA) versus the normalized board to ambient thermal parameter (θJB). The chip corner and the contact surface have a larger temperature difference, produce a mismatch phenomenon, and result in the destruction of the solder ball. © 2004 Wiley Periodicals, Inc. Heat Trans Asian Res, 33(6): 371–382, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/htj.20026

Thermal-Stress-Induced Failure in Memory Device Assembled Using Lead-on-Chip Die Attach Technique

Temperature cycling from -65°C to 150°C with a 30 min time interval was performed on high-density memory devices assembled in various packaging configurations utilizing a lead-on-chip (LOC) die attach technique. The experimental results showed that the double-sided adhesive tape used to attach the lead frame to the chip surface plays a significant role in defining the degree of thermal-stress-induced damage on the active chip surface. Three-dimensional stress simulation showed that the adhesive material can impose another shear component on thermal stresses induced by the plastic package body on the active chip surface. Thus, the tape tip should be located far from the chip corner to avoid the combined thermal shrinkage of the adhesive material and the plastic package body. Based on established mechanisms, it is suggested that the proper design of the double-sided adhesive tape may lead to improved reliability margins which provide more flexibility for package thickness control or package material selection.

Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants.

Failure criterion for moisture-sensitive plastic packages of integrated circuit (IC) devices: Application of von Kármán's equations with consideration of thermoelastic strains

The maximum value of the von-Mises stress in the molding compound at the chip corner is suggested to be used as a suitable failure criterion for moisture-induced plastic packages of integrated circuit (IC) devices. This criterion is able to reflect the role of various geometric and materials characteristics affecting the package propensity to moisture-induced failures during hightemperature reflow soldering. It is suggested also that the von-Mises stress be determined from the constitutive equations which are a generalization of the von-Kirmin equations for large deflections of plates with consideration of thermoelastic strains. The generalized von-Kimman equations are applied to the underchip layer of the molding compound and consider thermal effects associated with the thermal expansion (contraction) mismatch of the materials in the package, as well as with temperature gradients. The predicted stresses are in good agreement with experimental observations.The calculated von-Mises stresses can be used, particularly, for the development of “Figures of Merit” that would enable one to separate packages that need to be “baked” and “bagged” (or “rebaked” and “rebagged”) from those that supposedly do not. The calculated stresses can be used also to judge whether the qualification test conditions for sufficiently reliable packages (say, thick packages with small chips) could be safely “derated” to an actual factory humidity profile. Finally, the calculated von-Mises stress can be helpful in the selection of the most feasible molding compound for the given package design. A more reliable (and more expensive) material might be needed in the case of a thin package with a large chip, while a low cost compound can be successfully employed in the case of a thick package with a small chip.