Thermal-Stress-Induced Failure in Memory Device Assembled Using Lead-on-Chip Die Attach Technique

Abstract

Temperature cycling from -65°C to 150°C with a 30 min time interval was performed on high-density memory devices assembled in various packaging configurations utilizing a lead-on-chip (LOC) die attach technique. The experimental results showed that the double-sided adhesive tape used to attach the lead frame to the chip surface plays a significant role in defining the degree of thermal-stress-induced damage on the active chip surface. Three-dimensional stress simulation showed that the adhesive material can impose another shear component on thermal stresses induced by the plastic package body on the active chip surface. Thus, the tape tip should be located far from the chip corner to avoid the combined thermal shrinkage of the adhesive material and the plastic package body. Based on established mechanisms, it is suggested that the proper design of the double-sided adhesive tape may lead to improved reliability margins which provide more flexibility for package thickness control or package material selection.