Chip Components Research Articles

Tests and Analysis of Storage Life Extension of Hybrid Microcircuits for Aerospace Applications: A Case Study

Hybrid Microcircuits (HMCs) which bring about miniaturization with better performance and reliability are ideally suited for specific application where low volume requirement needed for aerospace missions. A large number of HMCs for varied applications are used in aerospace industry. HMCs generally use passive components and interconnections in thick film form, and active devices (MOSFETs, Transistor and Diode dice) and monolithic ICs (as bare chips) bonded to a substrate and are employed to carry out multiple functions. The die and other chip components utilized in making HMCs necessitated usage of hermetic sealing. The resulting HMCs consisting of multiple components are used as standalone EEE component. A general guideline of using HMCs for 9 years and re-screening after 3 years result in lot of constraint on resources and not viable in present scenario. The study conducted to find out the criticality and testing methodology for the extension of usable storage period. Comprehensive test plan consisting of variety of HMCs having varied processes, materials, density and various tests conducted as per the plan. This article details the various plans, choice of HMCs, testing results and analysis for the basis of extending the usable storage period of the HMCs for aerospace industry.

Reliability Testing of Recycled SMD Components Reused in E-Textiles after Ageing by Washing Cycles

This paper presents a method for recycling and reusing SMD chip components in e-textiles using a special contacting technique. The method involves using a UV-curable, non-conductive acrylic adhesive to connect SMD components onto electrically conductive textile stretchable ribbons. At the end of the product’s life-cycle, the components are removed from the ribbon and reused to manufacture new products. The recycling procedure involves several steps, including disassembly, inspection, cleaning, repair, and reassembly of components. The results of an experiment testing the electrical resistance of new and reused components after washing and drying cycles showed that electrical resistance of reused joints did not significantly deteriorate compared to new joints. The reused components maintain their functionality and performance, suffering no significant impairment. They perform comparably to new components, even after repeated washing and drying cycles. The method offers several benefits, including conservation of raw materials, minimization of waste, and reduction of production costs. It can also help mitigate component shortages. However, it is found that the suitability of this remanufacturing method varies with different types of components. Certain component types may be more susceptible to damage or even unsuitable for this method. The method is particularly beneficial for higher-value or components experiencing market shortages, demonstrating its potential to address urgent industry challenges while contributing to environmental sustainability.

Image defect classification of surface mount technology welding based on the improved ResNet model

In mass production, welding flaw detection in existing surface mount technology (SMT) has certain constraints, including its high costs, heavy workloads, and time-consuming processes. However, image classification technology using computer vision demonstrates high detection speeds and considerably reduced detection costs in flaw detection. Nevertheless, the increased integration of chip components on printed circuit boards (PCBs) and reduced component sizes pose challenges for flaw detection technology. Therefore, in this paper, an SMT welding image flaw classification model—that is, the ResNet-34-ECA model—based on an improved ResNet model, is proposed. Initially, the dataset is amplified using data amplification methods, such as stochastic rotation, increased data diversity, and enhanced model robustness. The ResNet34 model is then optimized using the light quantization efficient channel attention (ECA) module, resulting in higher classification accuracy. The experimental data in this study were collected using automated optical inspection (AOI) equipment, following the manual creation and amplification of the dataset. The experimental results showed that the baseline model accuracy increased by 0.22 in the augmented dataset, reaching 97.2%. Moreover, the ResNet-34-ECA model proposed in this paper could realize the classification of SMT welding image defects successfully; the overall classification accuracy of the improved ResNet image classification model was 0.01 higher than that of the baseline model, reaching 98.2%. Consequently, the proposed model proves to be better than other models in defect classification on this dataset, providing an accurate classification of SMT welding image defects.

Use of internet of things (IOT) on fish feeding tools with nodemcu

In everyday life whether in the city or in the countryside, there are lots of fish keepers in both large, medium sized ponds or small ones. Raising fish is an activity people who are very popular from the past until now, because ease of maintenance and care that makes most people want to cultivate fish. Fish kept in considered pond must give time to feed so that the fish requires a regular and continuous feeding schedule. ESP8266 NodeMCU is an integrated chip component that designed for today's connected world. these chips offers a complete, unified Wi-Fi networking solution that can used as an application provider or to sell all functions Wi-Fi networking to other application processors. One of its uses namely as an Automatic Fish Feeder Using ESP8266 Based on the Internet of Things (IOT). By using the components of the tool above as well as some supporting software When the tool runs, the fish feeder can automatically work in accordance with the schedule options that have been previously arranged, and capable displays data to web pages in the form of notifications when feed has been given and when the reservoir is empty or exhausted.

Solder Joint Geometry Effects on Thermomechanical Fatigue Lifetime of End-Capped Chip Component Assemblies

Solder Joint Geometry Effects on Thermomechanical Fatigue Lifetime of End-Capped Chip Component Assemblies

Electrochemical Metallic Ion Migration Property of Multi-Layer Ceramic Capacitor for Car Electronics

As the use of electrical components in automobiles increases, the occurrence of electorchemical metallic ion migration (ECM), which is one of the causes of various failures in electrical components, is also increasing. Therefore, in this study, 1608 MLCC chip components were used for temperature-humidity-bias (THB) tests at 65℃/85%R.H., 65℃/95%R.H., and 85℃/85%R.H. Three types of THB tests were conducted for 2,934 h. For the THB test, voltages of 3.3, 12 and 24 V were applied, and real-time resistance of MLCCs were measured at every 40 mms intervals. During the ECM test, the ECM occurrence time was measured by monitoring the insulation resistance of between the electrode of MLCC under each THB test conditions. The failure criteria for ECM occurrence were 106 Ω or less, and the time when it occurred more than twice was judged as the ECM failure criteria. Based on the ECM occurrence time, the mean life time of ECM occurrence according to temperature, humidity and applied voltage conditions was derived through Weibull statistical analysis. Finally, we compared and analyzed the sensitivity of MLCC components to ECM generation under use environment of automotive electronics.

When IC meets text: Towards a rich annotated integrated circuit text dataset

Automated Optical Inspection (AOI) is a process that uses cameras to autonomously scan printed circuit boards for quality control. Text is often printed on chip components, and it is crucial that this text is correctly recognized during AOI, as it contains valuable information. In this paper, we introduce ICText, the largest dataset for text detection and recognition on integrated circuits. Uniquely, it includes labels for character quality attributes such as low contrast, blurry, and broken. While loss-reweighting and Curriculum Learning (CL) have been proposed to improve object detector performance by balancing positive and negative samples and gradually training the model from easy to hard samples, these methods have had limited success with one-stage object detectors commonly used in industry. To address this, we propose Attribute-Guided Curriculum Learning (AGCL), which leverages the labeled character quality attributes in ICText. Our extensive experiments demonstrate that AGCL can be applied to different detectors in a plug-and-play fashion to achieve higher Average Precision (AP), significantly outperforming existing methods on ICText without any additional computational overhead during inference. Furthermore, we show that AGCL is also effective on the generic object detection dataset Pascal VOC. Our code and dataset will be publicly available at https://github.com/chunchet-ng/ICText-AGCL.

Finite element modeling and analysis method for predicting and optimizing the warpage of construction before flip chip bonding in System-on-Wafer process flow

As one of the solutions to surpass the limitations of Moore's Law in the post-Moore era, System-on-Wafer (SoW) technology provides the capability to integrate multiple chip components onto a single silicon wafer. A new high-density integrated SoW solution is discussed in this article. However, significant warpage can result from mismatches in the coefficients of thermal expansion (CTE) of different materials in a 12-in. wafer, presenting considerable challenges for the flip chip (FC) bonding, installation of power delivery and heat dissipation systems. Severe warpage can directly lead to the failure of the entire system. Therefore, pre-assessment and optimization of the warpage are crucial. This paper proposes a multi-scale modeling approach to assess the wafer warpage prior to FC bonding in the SoW fabrication process. To evaluate the accuracy of the modeling approach, a dummy die to thinned wafer and molding (DDTWM) was first designed and fabricated. The sole distinction in fabrication process between DDTWM and SoW is the absence of through silicon via (TSV) and backend of line (BEOL) metal traces. The simulation and experiment for DDTWM achieve a good level of consistency. In addition, following the completion of warpage simulations on the actual SoW structure prior to FC bonding, utilizing the same modeling approach, we proceeded to perform a Response Surface Methodology (RSM) analysis on several crucial parameters that exert influence on warpage. Subsequent to analyzing the results, optimization simulations were executed, underscoring the significant instructive value of RSM analysis in optimizing warpage within the structure prior to FC bonding in the SoW manufacturing process. This work offers an effective solution for predicting and mitigating substrate warpage prior to FC bonding in the SoW fabrication process, contributing to comprehensive warpage control.

(Invited) smart Wearable Electronics for Chronic Disease Management

60% of Americans live with at least one chronic disease. These diseases and associated comorbidities are now the leading causes of death in the United States. Effective management of complex chronic diseases requires body-wide, long-term, accurate, and continuous monitoring of multiple physiological signals from wearable devices to precisely determine the pathological state. These wearable physiological signal monitoring can dramatically reduce the demand of physician visiting and increase patients’ engagement and treatment adherence rate. Although wearable bioelectronic devices have shown huge potential in chronic disease management, existing technology still mostly relies on rigid chip components, where the interface between chips and skin/tissue has been a bottleneck that limits the system performance (noise, robustness etc). To address these challenges, my research has been involved in the exploration of rational system design concepts, material and device fabrication innovation, and tailored algorithms to enable smart wearable electronics that targets next-generation chronic disease management.Here I would like to discuss two of my developed technology platforms to elaborate the concept of smart wearables. First, I will describe a body area sensor network technology platform. In the system design concept side, this technology utilizes a novel wireless hybridization strategy and an unconventional detuned RFID working regime that provide an ideal skin interface. In the material/device side, this system integrates several skin-conforming polymer-based soft devices (ring oscillators, RF diodes, antennas, transistors etc.) as an integrated soft multimode sensing sticker. (1,2) Next, I will describe a wireless closed-loop smart bandage that can accelerate and monitor the wound healing process. (3) Such smart bandage also integrates new design concepts (wireless, battery-free design that combines both sensing and stimulation), novel materials (low-impedance, high-toughness, and tunable adhesion hydrogel as skin interface) and closed-loop control algorithms. Overall, the developed technology platform could assess multiple health outcomes and treatment responses to various chronic diseases. Ultimately, this technology will help to reduce chronic disease burden, lower medical costs, and provide a better quality of life for patients.

Directional movement of gold nanoparticles on the silicon substrate due to the Laplace pressure: A molecular dynamics simulation study

Due to superior ductility, oxidation resistance, and conductive properties, gold nanoparticles are widely used in semiconductor devices. From printing inks to electronic chips, gold nanoparticles are widely used as conductors. Nowadays, with the size of electronic chips getting smaller, gold nanoparticles have become an essential component in chip design. For example, they can connect resistors, conductors, and other electronic chip components. However, interactions of gold nanoparticles with curved substrates at high temperatures have rarely been studied. In our study, we simulated interactions of gold nanoparticles at high temperatures on a curved silicon substrate. It is observed that at above the metlting point, gold nanoparticles moved directionally under the effect of curvature gradients, and the curved surface can be used to control the coalescence of gold nanoparticles. The size, temperature of gold nanoparticles, and curvature gradients of the substrate are altered to observe their effects on gold nanoparticle movement. According to the results, we conclude that surface curvature gradients induce the Laplace pressure, and the Laplace pressure drives liquid gold nanoparticles to move directionally.

Planar fiber-chip-coupling using angle-polished polarization maintaining fibers

We report on our latest developments of a planar fiber-chip-coupling scheme, using angle polished, polarization maintaining (PM) fibers. Most integrated photonic chip components are polarization sensitive and a suitable way to launch several wavelength channels with the same polarization to the chip is the use of PM fibers. Those impose several challenges at processing and handling to achieve a stable, permanent, and low-loss coupling. We present the processing of the fibers in detail and experimental results for our planar and compact fiber-chip-coupling technique.

A machine‐learned microvasculature optimizes physiological insulin secretion in a vascularized pancreas‐chip

Microphysiological systems have gained increasing attention for their applications in drug discovery and testing, toxicity screening, and more recently disease modeling. However, microvascular networks are rarely incorporated into these devices despite being a major component of almost all tissues of the body. Of the reports integrating these networks, many use different quantification tools and fail to relate these quantifications to the biological function of the networks. Here, we standardized vasculature engineering by first generating 500 samples of microvascular networks‐on‐chips composed of different endothelial cell densities and sources, supporting cells, growth factors, and extracellular matrices. For each sample, 10 individual morphological metrics were generated using a peer‐reviewed, open‐source network quantification tool. Simultaneously, the mass transport of each sample was quantified using numerical simulation, resulting in a continuous value representing the biological function of each sample. Using machine learning, we then developed models using neural network regression methods that related the morphological metrics with the simulated biological function. Further, we identified which metrics most significantly impact the mass transport, as well as the integrable chip components that optimized mass transport and its related morphological metrics. Finally, we demonstrated how these optimizations lead to the vascularization of a pancreas microenvironment featuring insulin‐secreting islet cells. Further, vascularization rescues insulin secretion when pancreas‐chips are placed in hypoxia, demonstrating that the integration of microvascular networks plays a crucial role in the oxygenation and maintenance of a tissue‐specific microphysiological system.

Low‐Voltage Low Noise Figure Down‐Conversion Mixer for Band #1 of MB‐OFDM System in 180 nm Complementary Metal Oxide Semiconductor Technology

Low‐voltage design is a challenge for Gilbert cell‐based mixers due to stacking transconductance and switching stage. This work addresses this issue by proposing a design of a low‐voltage down‐conversion mixer for band #1 of multiband orthogonal frequency division multiplexing (MB‐OFDM) system in 180 nm complementary metal oxide semiconductor (CMOS) technology. The mixer is tuned at band #1 at RF frequency of 3.432 GHz and IF frequency of 264 MHz. The proposed mixer uses folded cascode connection of LO and RF in order to increase headroom and to reduce the DC supply voltage for low‐voltage operation. Common gate configuration is used at RF transconductance stage to enhance the input bandwidth of the mixer. RF and LO ports are matched to 50 Ω using differential T and LC matching, respectively. The resistive source denegation technique is used to linearize transconductance with respect to the bias point. The common source stage is used at the IF port as a buffer cum matching circuit it. The simulation results of the mixer show the maximum conversion gain of 9.76 dB, 1 dB compression point (P1dB) of ‐16.25 dBm, the third‐order input intercept point (IIP3) of ‐4.70 dBm, an SSB noise figure of 9.036 dB, and S11of ‐19.490 dB at the supply voltage of 1.2 V. Excluding off chip components, proposed mixer records an active area of 926.35 μm2.

Sustainable Self-Cooling Framework for Cooling Computer Chip Hotspots Using Thermoelectric Modules

The heat generation from recent advanced computer chips is increasing rapidly. This creates a challenge in cooling the chips while maintaining their temperatures below the threshold values. Another challenge is that the heat generation in the chip is not uniform where some chip components generate more heat than other components. This would create a large temperature gradient across the chip, resulting in inducing thermal stresses inside the chip that may lead to a high probability to damage the chip. The locations in the chip with heat rates that correspond to high heat fluxes are known as hotspots. This research study focuses on using thermoelectric modules (TEMs) for cooling chip hotspots of different heat fluxes. When a TEM is used for cooling a chip hotspot, it is called a thermoelectric cooler (TEC), which requires electrical power. Additionally, when a TEM is used for converting a chip’s wasted heat to electrical power, it is called a thermoelectric generator (TEG). In this study, the TEMs are used for cooling the hotspots of computer chips, and a TEC is attached to the hotspot to reduce its temperature to an acceptable value. On the other hand, the other cold surfaces of the chip are attached to TEGs for harvesting electrical power from the chip’s wasted heat. Thereafter, this harvested electrical power (HEP) is then used to run the TEC attached to the hotspot. Since no external electrical power is needed for cooling the hotspot to an acceptable temperature, this technique is called a sustainable self-cooling framework (SSCF). In this paper, the operation principles of the SSCF to cool the hotspot, subjected to different operating conditions, are discussed. As well, considerations are given to investigate the effect of the TEM geometrical parameters, such as the P-/N-leg height and spacing between the legs in both operations of the TEC mode and TEG mode on the SSCF performance.

Microstrip Impedance Management through Multilayer PCB Stack-Up: Discontinuity Compensation Voids with Asymmetric Dielectrics

To process high-frequency signals on a printed circuit board (PCB), it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0. Modern PCBs are complex multilayer designs, utilizing either only high-end laminates, low-end laminates, or a combination of both. The on-board component footprints usually have larger pads that become discontinuities and corrupt the impedance of critical traces. One way to address this issue is to include reference plane cutouts as a measure of compensation. This paper aims to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts. The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs that strictly comprise high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice. S-parameter measurements are performed and confirmed by time domain reflectometry (TDR) measurements.

Research on Furnace Temperature Curve Based on Linear Regression Model

With the rapid development of social science and technology, various industries have higher and higher requirements for the quality of electronic products. SMT surface mount technology is the most popular process in the electronics assembly industry, and reflow soldering is one of the SMT mounting processes. Reflow soldering is mainly used to solder the circuit boards with components already attached. The solder paste is melted by heating to fuse the chip components and the circuit board pads together, and then the solder paste is cooled by the cooling of the reflow soldering, and the components are soldered. The plates are solidified together, and the furnace temperature curve records the temperature changes of the circuit board during this process. This article focuses on the printed circuit board welding production problem, through optimizing the furnace temperature curve for high-efficiency and quality-guaranteed production, and researches on the changes of the furnace temperature curve at different temperatures.

Temperature-regulated surface charge manipulates ionic current rectification in tapered nanofluidic channel

Diverse ionic current rectification methods for nanofluidic chips have recently emerged. Herein, we theoretically demonstrate that by applying a temperature gradient to the aqueous solution, the ionic rectification property of a tapered nanochannel can be manipulated by applying temperature gradients from the tip to base and vice versa. Our modeling results reveal that the rectification ratio can be significantly enhanced by applying a temperature increment from the base to tip, whereas the rectification ratio is significantly suppressed by applying a reverse temperature gradient. In addition to the solution temperature, we also investigated the influence of bulk ionic strength and tip height on the rectification ratio, thereby providing overlapping and non-overlapping regimes of electrical double layers. We demonstrate that the rectification behavior of a tapered nanochannel is determined by the overlapping regime of the electrical double layer at the tip of the nanochannel. Moreover, we propose a semi-analytical solution that can capture numerical results with the same order of magnitude. We expect that the modeling results of this contribution can provide a direction for understanding ionic transport across geometrically and thermally asymmetrical media, which could find applications from energy conversion to logical nanofluidic chip components.

MLCC Solder Joint Property with Vacuum and Hot Air Reflow Soldering Processes

After the joining of small 1005 and 0603 multilayer ceramic capacitor (MLCC) components for a semiconductor package using Type 4 (T4) and Type 7 (T7) Sn-3.0Ag-0.5Cu (SAC305), T4 Sn-1.0Ag-0.5Cu (SAC105), and T4 Sn-0.3Ag-0.7Cu (SAC0307) solder pastes, the differences between hot air reflow and vacuum soldering processes were compared in terms of void content, shear strength, and microstructure. Results showed that the hot air reflow soldering process exhibited a stable joint with a void content of 5% or less, and the vacuum soldering condition significantly reduced the void content of the solder joint as the soldering proceeded in a vacuum state. The shear strength of the SAC305 solder joint with the same powder particle size was measured to be greater for the shear strength of the vacuum soldered joint as compared to the reflow process. The vacuum soldering process was effective in removing voids during the void joining process and contributed to an improved joint strength of the solder joint by reducing the void content. When the same soldering process was applied using the 1005 MLCC chip component, the bonding strength of the T4 SAC305 solder was slightly higher than those of the SAC105 and SAC0307 solders. However, the overall initial bonding strengths were similar. The e ffects of Ag content within 0.3-3.0 wt% on the initial bonding strengths of the solders were judged to be the same. Diverse Cu6Sn5, Ag3Sn, (Ni,Cu,Pd)3Sn4, (Cu,Ni)6Sn5, NiP, and Ni3P intermetalli ccompounds (IMCs) were formed at the interfaces between the electroless nickel/electroless palladium/immersion gold finish substrate and SAC solder joint. The IMC types were constant regardless of Ag content and solder type, and the IMCs contributed to the initial solder joint strength.

The DAQ and control system for JadePix3

The silicon pixel sensor is the core component of the vertex detector in the Circular Electron Positron Collider (CEPC). The JadePix3 is one of the chips designed to study the performance and design of pixel sensors. The chip is a design of the full-function large-size chip based on CMOS technology. To test all the functions and the performance of this chip, we designed a test system based on the IPbus framework. The test system controls the parameters and monitors the status of the pixel chip and off-chip components. The IPbus block read/write speed is extended by jumbo frame feature integration to the IPbus suite for meeting the readout specifications of the JadePix3. The robustness, scalability, and portability of this system have been verified by pulse test, cosmic test and laser test in the laboratory. This paper describes the JadePix3 DAQ and control system, the integration tests, results and performance are included.

A Transformer using two RDL metal layers based on Fan-Out Panel Level Package Technology

Under the background that electronic products have been developing in the direction of being smaller, lighter and cheaper, the packaging of chip components has also been continuously improved. Fan-out panel-level package (FOPLP) is one of the latest development trends in microelectronics package, which can achieve higher productivity and lower costs. A planar toroidal spiral transformer is designed based on Fan-Out Panel Level Package technology. The transformer is constructed by two RDL layers provided by the packaging process. The size of the proposed transformer is 434um×434um. The simulated primary and secondary inductance is 2.5nH and 2.5nH respectively. The coupling factor of the transformer is 0.845. The quality factor of the transformer is higher than 800 during the entire working frequency range. The self-resonant frequency of the present transformer is 20 GHz. Compared to the on-chip counterpart, the transformer designed based on Fan-Out Panel Level Package technology can achieve higher coupling factor and quality factor. Therefore, the proposed transformer can save chip size and reduce the cost through avoiding using area hungry passive on chip transformer.