Microstrip Impedance Management through Multilayer PCB Stack-Up: Discontinuity Compensation Voids with Asymmetric Dielectrics

Aleksandr Vasjanov,Vaidotas Barzdenas

doi:10.3390/sym13101771

Aleksandr Vasjanov, Vaidotas Barzdenas

Open Access

https://doi.org/10.3390/sym13101771

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Journal: Symmetry	Publication Date: Sep 23, 2021
Citations: 4	License type: CC BY 4.0

Affiliation: Vilnius Gediminas Technical University

Abstract

To process high-frequency signals on a printed circuit board (PCB), it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0. Modern PCBs are complex multilayer designs, utilizing either only high-end laminates, low-end laminates, or a combination of both. The on-board component footprints usually have larger pads that become discontinuities and corrupt the impedance of critical traces. One way to address this issue is to include reference plane cutouts as a measure of compensation. This paper aims to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts. The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs that strictly comprise high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice. S-parameter measurements are performed and confirmed by time domain reflectometry (TDR) measurements.

Highlights

If the multiple layer cutout contains a number of different laminates, some of which are high-end low-loss, and others are cheaper higher-loss, the uniformity of the overall structure is affected by the quantity of each type of dielectric material in that stack-up
A six-layer printed circuit board (PCB) comprising two types of dielectric materials with different properties was designed, simulated, and fabricated in order to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts
The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs, which only consist of high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice

Summary

Introduction

There is no doubt that this industrial revolution will be based on the rapidly developing 5G technologies and their infrastructure [3,4,5], which naturally leads to solving the challenge of manufacturing cost reduction in electronic devices These include various engineering problems, such as dealing with high component densities, implementing RF and digital high-frequency circuits without compromising basic parameters, reducing their electromagnetic compatibility (EMC) emission level, and hardening EMC susceptibility, all while operating in low energy consumption conditions. To process high-frequency signals on a PCB, it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0 (e.g., 50 Ω) PCB track width and impedance This is not an easy thing to do, as the geometry of modern chip packs is rapidly declining and becoming significantly smaller than the width of a standard. Microwave Engineering, 4th ed.; John Wiley & Sons, Inc.: Hoboken, NJ, USA, 2012; pp. 261–267

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