Chip Area Overhead Research Articles

A training method for deep neural network inference accelerators with high tolerance for their hardware imperfection

We propose a novel training method named hardware-conscious software training (HCST) for deep neural network inference accelerators to recover the accuracy degradation due to their hardware imperfections. Existing approaches to the issue, such as the on-chip training and the in situ training, utilize the forward inference data that are obtained by the inference accelerators for the backpropagation. In the approaches, since the memory devices that are used for the weights and the biases are to be switched after each epoch, the total number of the switching in the training process grows too large to avoid the problems of endurance limitation, nonlinearity and asymmetry in the switching of the nonvolatile memories used for the weights and the biases. The proposed training method is totally conducted by software whose forward inference path and backpropagation reflect the hardware imperfections, overcoming all the above problems. The HCST reformulates the mathematical expressions in the forward propagation and the gradient calculation with the backpropagation so that it replicates the hardware structure under the influence of variations in the chip fabrication process. The effectiveness of this approach is validated through the MNIST dataset experiments to manifest its capability to restore the accuracies. A circuit design is also disclosed for measuring the offset voltages and the open loop gains of the operational amplifiers used in the accelerator, showing that the chip area overhead is minor.

A 20.65-to-40.55 GHz Dual-Core Quad-Mode VCO With Mode-Independent Transformer-Switching Technique in 65-nm CMOS

This paper proposes a dual-core quad-mode millimeter-wave (mm-wave) voltage-controlled oscillator (VCO) using a compact multi-mode LC network with a modeindependent switched transformer technique. On top of the dualmode main LC tank, the mode-independent switched transformer technique introduces two additional oscillation modes, further extending the frequency tuning range with a small chip area overhead, while the mode-independent feature reduces the cost of switch off-capacitance compared with the conventional switched transformers. Implemented in 65nm CMOS process, the proposed VCO achieves a measured octave frequency tuning range from 20.65 to 40.55 GHz. The measured best phase noise is -131.04 dBc/Hz at 10 MHz offset from 20.65 GHz. The measured best figure-of-merit (FoM) is 187.25 dBc/Hz at 10 MHz offset from 26.66 GHz, corresponding to a figure-of-merit of tuning range and area (FoMTA) of 216.72 dBc/Hz thanks to the proposed compact multi-mode LC network and the mode-independent switched transformer technique. The VCO consumes 9.75-to-18.85 mW from a 0.65 V supply voltage. The core area is 0.048 mm2.

Generation of New Low-Complexity March Algorithms for Optimum Faults Detection in SRAM

Memory BIST implements March test techniques extensively for testing embedded memories on a chip. A high-complexity test algorithm like the March MSS (18N) can guarantee the detection of all unlinked static faults in SRAM. In contrast, March algorithms with lower complexity can be used to reduce test costs and chip area overhead. Still, they have poor coverage of faults identified in the nanometer process technologies. Subsequently, a balance between the fault coverage and the test cost is necessary. This paper presents a method to generate new March algorithms that provide optimum coverage on faults introduced by the nanometer process technologies. It was achieved by developing automated software to generate the new Data Background sequence and rearrange the existing March algorithms’ test operations to remove redundancies and enable the sensitization and detection of the intended faults while preserving their complexities. Comprehensive fault detection analyses were conducted to assess their fault coverages and to find any removable redundant test operations. The proposed method produced new March AZ1 and March AZ2 algorithms, with 13N and 14N complexity, respectively, that provide optimum coverage of the targeted faults. They were successfully implemented in the Memory BIST controllers, and their functionalities were validated via simulations.

Capacitive Feedbacked Cold-Phase Compensator Analog Pre-Distorter and PAE Enhancer for K-Band CMOS PAs

A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD’s compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors’ knowledge, is the highest reported enhancement of the linearizers of k-band PAs.

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

As process scaling continues, DRAM is getting more vulnerable to errors. System companies and DRAM vendors have introduced ECC to protect DRAM against growing errors. ECC, however, should be combined with a repair mechanism to prevent non-transient faults from repeatedly producing errors and to prevent overlapping faults from accumulating into more severe errors. We propose a novel approach to repair memory and improve reliability with minimal overheads. On-die Dynamic Remapping Cache (DRC) minimizes the repair overheads by focusing on active faults. Most intermittent faults (e.g., Variable Retention Time) generate errors occasionally, and the number of active faults at any one time is significantly lower than the total. DRC tracks the activity and severity of faults at run-time and uses a small cache inside a DRAM to remap active faults. This efficiency enables aggressive remapping of bit faults, which eliminates fault accumulations and improves reliability. Our evaluation shows DRC can provide much stronger protection than the state-of-the-art protection schemes with no performance degradation and a negligible chip area overhead.

Soft-core embedded FPGA based system on chip

Nowadays, there has been an intensive increase in embedded systems complexity. So that optimization and performance development become an interesting topic to study. In this proposal, the main problem to solve is to make the possibility to get more flexibility, to reduce cost and to improve performance. Considering this fact, we introduce in this paper a reconfigurable component integrated into Cortex M0 based System on Chip (SoC) which has the form of embedded FPGA. To the best of our knowledge, this is the first reconfigurable SoC composed of Tree-based embedded FPGA. Besides, we explored the different ways to reach the integration and the different steps. Then, we compared reconfigurable SoC with another developed SoC which contains many hardware accelerators which are a set of popular benchmarks in terms of performance and area. Finally, we take a popular error correction algorithm “RS-Encoder” as a test case. We made the profiling of this software application in order to compare the reconfigurable SoC with a classic SoC in terms of run-time. Preliminary results were presented and showed that the eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS Encoder application.

Efficient Hardware Architectures for 1D- and MD-LSTM Networks

Recurrent Neural Networks, in particular One-dimensional and Multidimensional Long Short-Term Memory (1D-LSTM and MD-LSTM) have achieved state-of-the-art classification accuracy in many applications such as machine translation, image caption generation, handwritten text recognition, medical imaging and many more. However, high classification accuracy comes at high compute, storage, and memory bandwidth requirements, which make their deployment challenging, especially for energy-constrained platforms such as portable devices. In comparison to CNNs, not so many investigations exist on efficient hardware implementations for 1D-LSTM especially under energy constraints, and there is no research publication on hardware architecture for MD-LSTM. In this article, we present two novel architectures for LSTM inference: a hardware architecture for MD-LSTM, and a DRAM-based Processing-in-Memory (DRAM-PIM) hardware architecture for 1D-LSTM. We present for the first time a hardware architecture for MD-LSTM, and show a trade-off analysis for accuracy and hardware cost for various precisions. We implement the new architecture as an FPGA-based accelerator that outperforms NVIDIA K80 GPU implementation in terms of runtime by up to 84× and energy efficiency by up to 1238× for a challenging dataset for historical document image binarization from DIBCO 2017 contest, and a well known MNIST dataset for handwritten digits recognition. Our accelerator demonstrates highest accuracy and comparable throughput in comparison to state-of-the-art FPGA-based implementations of multilayer perceptron for MNIST dataset. Furthermore, we present a new DRAM-PIM architecture for 1D-LSTM targeting energy efficient compute platforms such as portable devices. The DRAM-PIM architecture integrates the computation units in a close proximity to the DRAM cells in order to maximize the data parallelism and energy efficiency. The proposed DRAM-PIM design is 16.19 × more energy efficient as compared to FPGA implementation. The total chip area overhead of this design is 18 % compared to a commodity 8 Gb DRAM chip. Our experiments show that the DRAM-PIM implementation delivers a throughput of 1309.16 GOp/s for an optical character recognition application.

Power transition X filling based selective Huffman encoding technique for test-data compression and Scan Power Reduction for SOCs

Due to the excessive utilization of memory, data compression is an evergreen research topic. Realizing the constant demand of compression algorithms, this article presents a compression algorithm to analyse the digital VLSI circuits for constraint optimization, such as test data volume, switching power, chip area overhead and processing speed of testing. This article proposes a new power transition X filling based selective Huffman encoding technique, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing. The performance of the proposed work is examined with the help of ISCAS benchmark circuits. Initially, the test set is occupied by using the power transition X filling technique to replace the don't care bits and the filled test set is further encoded by selective Huffman encoding technique. The experimental results show that the proposed power transition X filling based selective Huffman encoding gives effective results compared to the related data compression techniques with minimal time and memory consumption.

85–110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceivers

Two CMOS nonreciprocal components: 1) an isolator and 2) a circulator are demonstrated at 100-GHz band for full-duplex transceivers for ultra-high-data-rate wireless communication. The proposed nonreciprocal structures are based on a time-domain modulation by signals at around one-sixth of the RF frequencies and spatial duplexing throughout their RF signal paths, demonstrating over 45-dB isolation in a bandwidth of 1.5 GHz over the tuning range of 85-110 GHz. In the presented isolator, two capacitive mixers together with a biasing network form a resonant type of wideband matching for lower loss. An improved delta topology is proposed for the circulator design which reduces the schematic complexity and chip area overhead. Implemented in a 65-nm CMOS with a chip area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively, both the isolator and the circulator achieve over 45-dB isolation and >10 dB return losses throughout the entire bandwidth. A maximum of 4.5- and 5.6-dB insertion losses (ILs) are achieved by the isolator and circulator, respectively.

A Fully on-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses

This paper presents a fully on-chip mixed-mode low-dropout (LDO) regulator with improved regulation and transient responses. With the help of the digital regulation part, the supported maximum load current is significantly improved, while the chip area overhead is very small. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. A proof-of-concept LDO design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V, and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA, which is more than 480% improved over the traditional design without digital assistance.

State reduction for efficient digital calibration of analog/RF integrated circuits

Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit's performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit's operation through built-in tuning knobs. Digital calibration--that refers to the case of discrete tuning knob settings--is performed by switching to a circuit's state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology.

Area efficient remote code execution platform with on-demand instruction manager for cloud-connected code executable IoT devices

An energy-area efficient cloud-connected software execution architecture in IoT sensor processor is proposed. A remotely installed sensor device such as an environmental activity monitor is commonly implemented using the conventional embedded processor only providing the fixed services, which includes statically compiled embedded software in on-chip flash memory. Instead of conventional on-chip flash memory for an instruction code area, we adopt an virtually mapped internal memory concept to realize cloud-connected software execution, in where the remote storage area via the IoT platform is indirectly mapped onto the physical address space of the instruction memory using a dynamic address translation technique. The proposed cloud-connected architecture of the system enables on-demand code execution for the instructions, which are fetched from the cloud-side remote storage area in the runtime, instead of using a directly-connected on-chip instruction bus. The proposed storage-less approach may be adopted to reduce the high access current and large chip area overhead by eliminating the on-chip code flash memory. To reduce the access current overhead in order to retrieve the requested instruction, a small-sized RAM scratch pad is adopted for retaining the hot-spot instruction code and early filled with pre-estimated instruction sector. The experimental results show that the proposed technique reduces the energy consumption and packet delay of an IoT device for executing the remote embedded software, as well as the reduced chip area by realizing a storage-less sensor architecture.

Efficient Remote Software Management Method based on Dynamic Address Translation for IoT Software Execution Platform in Wireless Sensor Network

Background/Objectives: In this paper, an efficient remote code execution technique is proposed to implement a storage-less sensor in the Internet-of-Things (IoT) paradigm. Methods/Statistical Analysis: To realize a flexible code update mechanism and to optimize the use of an IoT device in terms of utilizing its various functions, we adopt the concept of remote on-demand code execution (ROCE) to implement a storage-less sensor. Findings: Instead of using a conventional on-chip flash memory for an instruction code, an instruction memory is used wherein the remote storage area based on the IoT platform is virtually mapped onto the address space of the instruction memory using a dynamic address translation technique. The proposed storage-less approach using the remote resource as a virtual code space may be adopted to reduce the high access current and chip area overhead of an on-chip code flash memory. Application/Improvements: The proposed technique reduces the energy consumption and the packet delay of an IoT device for executing the remote embedded software, as well as realizes a storage-less sensor architecture.

Characterizing and Exploiting Small-Value Memory Instructions

This paper exploits small-value locality to accelerate the execution of memory instructions. We find that small-value loads—loads with small-value operands of 8 bits or less—are common across 52 applications from the desktop, embedded, and media domains. We show that the relative occurrences of small-value loads remain fairly stable during the program execution. Moreover, we establish that the frequency of small-value loads are almost independent of compiler and input data. We then introduce the concept of small-value caches (SVC) to compactly store small-value memory words. We show that SVCs provide significant speedup and reduce the overall energy dissipation with negligible chip-area overhead.

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by the more frequent appearance of soft errors are becoming critical for future embedded multiprocessor systems design. State-of-the-art techniques for soft error protections targeting multiprocessor systems result either high chip cost and area overhead or high performance degradation and energy consumption, and do not fulfill the increasing requirements for high performance and dependability. In this article we present a systematic approach, that is, the Sensor Networks-on-Chip (SENoC), to collaboratively and efficiently manage on-chip applications and overcome reliability threats to Multiprocessor Systems-on-Chip (MPSoC). A hardware-software collaborative approach is proposed to solve soft error problems: a hardware-based on-chip sensor network is built for soft error detection, and a software-based recovery mechanism is applied for soft error correction. A two-step scheduling scheme is presented for reliable application and chip management, combining an off-line static optimization stage for application performance maximization and an online lightweight dynamic adjustment stage to handle runtime variations and exceptions. This strategy introduces only trivial overhead on hardware design and much lower overhead on software control and execution, and hence performance degradation and energy consumption is greatly reduced. We build a cycle-accurate simulator using SystemC, and verify the effectiveness of our technique by comparing performance with related techniques on several real-world applications.

Design of an Effective Charge Pump-Phase Locked Loops Architecture for RF Applications

and mixed architectures design with high performance suffered from many difficulties due to low power supply, consumption, and the trend toward reducing the size of the circuit. Currently, these performances are considered one of the main constraints in analog design. Characterized and designed of mixed circuits such as Charge Pump-Phase Locked Loops (CP- PLLs) is a challenge in mixed-signal integrated circuits design. In this paper, an effective CMOS CP-PLLs architecture for RF applications that operates at a low power supply 2V into a large range frequency is presented. The proposed CP-PLLs architecture has two novel design blocks which are respectively Phase Frequency Detector (PFD) and Voltage Controlled Oscillator (VCO). The key advantage of the two novel designs is that uses a simple circuit, provide more stable operation compared with other structures recently used and reduce the chip area overhead. Also, the novel VCO design solved the problems caused by recent structures. The CP-PLLs is designed and evaluated using electrical simulator tolls (ADS) with 0.35μm AMS CMOS technology. Simulations results show a good performance and the effectiveness of the proposed structure.

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2V, 65nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.

Time-Multiplexed Online Checking

There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for cost-sensitive applications. In this paper, we introduce a Time-Multiplexed Online Checking (TMOC) scheme using embedded field-programmable blocks for checker implementation, which enables various system parts to be checked dynamically in-field in a time-multiplexed fashion. The test quality analyses using a probabilistic model show that TMOC could maintain high fault coverage that is similar to traditional dedicated checkers. We conducted a case study of an H.264 decoder design that demonstrates our TMOC scheme provides a significant reduction in chip area and power overhead for online checkers at the cost of increased fault detection latency. We have successfully implemented and demonstrated our proposed TMOC scheme using a single Field-Programmable Gate Array (FPGA) chip.

Protection Circuit against Differential Power Analysis Attacks for Smart Cards

In this paper, we present a circuit that protects smart cards against differential power analysis attacks. The circuit is based on a current flattening technique, is designed using a standard 0.18-µm CMOS technology, and can be integrated on the same die or in the same package with the smart card microcontroller. We evaluate the current flattening performance and the effectiveness of the protection against differential power analysis attacks. Our analysis is based on transistor-level simulations in Cadence environment using experimental current traces collected from an 8-bit microcontroller for smart cards executing DES encryptions. The proposed circuit effectively protects against differential power analysis attacks with small chip area overhead and limited increased power consumption during the encryption cycles.

Local variable access behavior of a hardware-translation based Java virtual machine

Hardware bytecode translation is a technique to improve the performance of the Java virtual machine (JVM), especially on the portable devices for which the overhead of dynamic compilation is significant. However, since the translation is done on a single bytecode basis, a naive implementation of the JVM generates frequent memory accesses for local variables which can be not only a performance bottleneck but also an obstacle for instruction folding. A solution to this problem is to add a small register file to the data path of the microprocessor which is dedicated for storing local variables. However, the effectiveness of such a local variable register file depends on the size and the local variable access behavior of the applications. In this paper, we analyze the local variable access behavior of various Java applications. In particular, we will investigate the fraction of local variable accesses that are covered by the register file of a varying size, which determines the chip area overhead and the operation speed. We also evaluate the effectiveness of the sliding register window for parameter passing in context of JVM and on-the-fly optimization of local variable to register file mapping. With two types of exceptions, a 16-entry register file achieves coverages of up to 98%. The first type of exception is represented by the SAXON XSLT processor for which the effect of cold miss is significant. Adding the sliding window feature to the register file for parameter passing turns 6.2–13.3% of total accesses from miss to hit to the register file for the SAXON with XSLTMark. The second type of exception is represented by the FFT, which accesses more than 16 local variables for most of method invocations. In this case, on-the-fly profiling is effective. The hit ratio of a 16-entry register file for the FFT is increased from 44% to 83% by an array of 8-bit counters.