Capacitive Feedbacked Cold-Phase Compensator Analog Pre-Distorter and PAE Enhancer for K-Band CMOS PAs

Abstract

A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD’s compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors’ knowledge, is the highest reported enhancement of the linearizers of k-band PAs.