Check Codes Research Articles

Minimization of the Fading Effect in Indoor Wireless Communication using Coherent 16- Amplitude Phase Shift Keying with Regular Low Density Parity Check Code

Minimization of the Fading Effect in Indoor Wireless Communication using Coherent 16- Amplitude Phase Shift Keying with Regular Low Density Parity Check Code

An analysis and improvement of error control performance of IS-LDPC codes with a large number of subsets

Peak-to-Average Power Ratio (PAPR) is a major shortcoming of Orthogonal Frequency Division Multiplexing (OFDM) system. One attractive solution to this problem is Invertible-Subset Low-Density Parity Check (IS-LDPC) code. Although IS-LDPC codes perform distinctively in sense of controlling PAPR with low search complexity, their error control performance suffers from degradation when the number of invertible subsets increases. In this paper, the reasons for the aforementioned performance degradation are mathematically analyzed. Moreover, a heuristic search method is proposed to improve error control performance of IS-LDPC codes, while maintaining their good PAPR control performance, as well as low searching complexity.

Serially Concatenated Low-density Parity Check Codes as Compatible Pairs

Low-density parity checks (LDPC) codes are considered good performance error correction codes. However, decoder complexity increases with increasing code length. In this study, we introduce short-length serially concatenated LDPC codes. The proposed technique uses pairs of compatible LDPC codes that act as outer and inner serially concatenated codes. In this code pair, the inner code takes input that is the same length as the outer LDPC encoder output. This study examined two cases of LDPC codes as compatible pairs with low numbers of iterations and compared bit error rate (BER) performance to a standalone LDPC code with an additive white Gaussian noise channel. We also considered the quadrature phase shift keying QPSK, 16-quadrature amplitude modulation (QAM), and 64-QAM system modulation schemes. Simulation results demonstrate that the proposed system has good BER performance compared to a standalone LDPC code, the results summarized in table and performance curves.

Low Density Parity Check Codes Constructed from Hankel Matrices

In this paper, a new technique for constructing low density parity check codes based on the Hankel matrix and circulant permutation matrices is proposed. The new codes are exempt of any cycle of length 4. To ensure that parity check bits can be recursively calculated with linear computational complexity, a dual-diagonal structure is applied to the parity check matrices of those codes. The proposed codes provide a very low encoding complexity and reduce the stored memory of the matrix H in which this matrix can be easily implemented comparing to others codes used in channel coding. The new LDPC codes are compared, by simulation, with uncoded bi-phase shift keying (BPSK). The result shows that the proposed codes perform very well over additive white Gaussian noise (AWGN) channels.

Reduced decoding time of LDPC code using convolutional code with Vitrebi decoding in Underwater Communication

Low Density Parity Check code is the more efficient technique to attain the minimal error rate in the underwater channel. To reduce the processing delay in the LDPC decoding, convolutional code with high code rate is used. The result showed that the BER of 10-4 can be obtained with Eb/No value of 20 for code rate of ½ and 12 for code rate of 1/8. It is also showed in result that the decoding time is reduced one-third for data size of 500 and one-tenth for the data size of 1500 bits.

A Family Of Low Density Matrices In Lagrangian–Grassmannian

Abstract The aim of this paper is twofold. First, we show a connection between the Lagrangian- Grassmannian variety geometry defined over a finite field with q elements and the q-ary Low-Density Parity- Check codes. Second, considering the Lagrangian-Grassmannian variety as a linear section of the Grassmannian variety, we prove that there is a unique linear homogeneous polynomials family, up to linear combination, such that annuls the set of its rational points.

Efficient high throughput decoding architecture for non-binary LDPC codes

This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

Design of Low-Density Parity Check Codes for 5G New Radio

Turbo codes, prevalent in most modern cellular devices, are set to be replaced by LDPC codes as the code for forward error correction. This transition was ushered in mainly because of the high throughput demands for 5G New Radio (NR). The new channel coding solution also needs to support incremental-redundancy hybrid ARQ, and a wide range of blocklengths and coding rates, with stringent performance guarantees and minimal description complexity. In this article, we first briefly review the requirements of the new channel code for 5G NR. We then describe the LDPC code design philosophy and how the broad requirements of 5G NR channel coding led to the introduction of novel structural features in the code design, culminating in an LDPC code that satisfies all the demands of 5G NR.

LCPC error correction code for IoT applications

This paper presents a novel error detection and correction codes, called the Low Complexity Parity Check (LCPC) codes that detect and correct consecutive and non-consecutive bit errors. The proposed codes can be used as a Forward Error Correction (FEC) scheme for Internet of Things (IoT) applications and specifically Wireless sensor networks (WSNs). Besides, the LCPC codes have less complexity and lower memory requirement as compared to the Reed Solomon (RS) and Low Density Parity Check (LDPC) codes. The LCPC codes do not require reiteration in the decoding process as in LDPC codes. Moreover, Simulation results show that the proposed LCPC codes outperform the Hamming, RS and LDPC codes while keeping the computational complexity very low. This leads prolonged battery lifetime due to the reduced number of retransmissions, and thus makes the LCPC more suitable for numerous emerging IoT applications.

An unequal error protection scheme for non-binary LDPC using statistical QAM and prioritized mapping

Low Density Parity Check (LDPC) codes are among the most popular channel codes used nowadays because of their ability to achieve near channel capacity performances. However, with the ever-increasing demand for reliable transmission of data at higher data rates, there is a need to narrow down the gap between the performance of LDPC codes and the channel capacity. LDPC codes and Quadrature Amplitude Modulation (QAM) have been widely deployed in wireless communication standards such as the IEEE 802.11n and Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2). Recently, several Unequal Error Protection (UEP) schemes have been used to enhance the performance of LDPC codes. In this paper an UEP scheme is proposed for Non- Binary LDPC codes with QAM. The scheme uses the statistical distribution of the source symbols to obtain a more efficient statistical QAM constellation. Additionally, it uses the degree distribution of the nodes of the LDPC codeword to achieve prioritized QAM mapping. Simulations revealed that the proposed scheme can provide Eb/N0 gains of up to 0.78 dB and 1.24 dB with 16-QAM and 64-QAM respectively in the range BER?10-2.

Cross-Layer Based Error Control Technique for WSN with Modified Relay Node Selection and Corruption Aware Method

In Wireless Sensor Network, packet failure or error is to be controlled possibly. Based on that, we presented Cross-layer Based Error Control Technique for WSN in our previous work. In this paper, we present Modified relay node selection and corruption aware method for further improve the performance of the network. Modified relay nodes are selected using Markov chain decision process. Three relay selection methods are discussed in this paper. Those methods are “permanent”, “reactive”, and “adaptive”, which have various mandates for relay update. After the relay node selection, data packets are transmitted to the destination by selecting these relay nodes. At the receiver, the received data packet is verified whether it is corrupted or not using Received Signal Strength Indicator. If the received packet is corrupted, then the corrupted packet is encoded before re transmission using Low Density Parity Check Codes. Simulation results show that performance of this work is superior to our previous work in terms of delivery ratio and packet drop.

Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm

For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives high throughput. The proposed work has been implemented and tested on Xilinx Virtex 5 FPGA. The MATLAB result of LDPC decoder for low bit error rate (BER) gives bit error rate in the range of 10-1 to 10-3.5 at SNR=1 to 2 for 20 no of iterations. So it gives good bit error rate performance. The latency of the parallel design of LDPC decoder has also reduced. It has accomplished 141.22 MHz maximum frequency and throughput of 2.02 Gbps while consuming less area of the design.

Two-Side State-Aided Bit-Flipping Decoding of Generalized Low Density Parity Check Codes

A modified bit-flipping (BF) decoding algorithm is proposed for hard-decoding of generalized low- density parity-check codes over binary channels. This approach introduces an extra bit between the variable nodes and constraint nodes representing the decision reliability of each node. The local decoding failure is also analyzed to provide a reasonable treatment for the most of its causes. The approach is not in the direction of constructing codes with minimum trapping sets, but to reduce their effect in the decoder at a cost of little increase in the resources. The algorithm, which is called two-side state-aided BF, is shown by simulations to outperform previous BF algorithms in terms of error performance.

High performance gain demodulate system for hybrid fiber-coaxial

Gigabit capable of Hybrid Fiber-Coaxial (HFC) represented an increase. The goals of the next generation HFC system are to efficiently utilize the precious last 100m of the coaxial cable and to achieve a Gigabit transmission rate. This target demands higher requirements regarding the physical layer (PHY) throughput. Firstly, the PHY architecture of next generation HFC system is given in detail. Secondly, in order to meet challenging high PHY throughput, a class of Low Density Parity Check (LDPC) code is selected as the Forward Error Correction (FEC) scheme, the ultimate choice is made on the basis of system with a better bit error rate performance. Finally, this paper combines the characteristics of Gray code symbol mapping for Quadrature Amplitude Modulation (QAM) constellation to design a soft decision algorithm based on signal diversity. Especially in terms of power efficiency, this algorithm can beyond the performance of log-MAP algorithm.

Multi-user Communication Based OFDM-UWB System under Gaussian and Non-Gaussian Noisy Channel

For a multiuser Ultra Wide Band (UWB) system, the performance is mainly limited by inherent noise and interferences such as Multiple Access Interference (MAI) and Inter Symbol Interference (ISI) which are poorly approximated by a Gaussian distribution because of their impulsive nature. A combination between Orthogonal Frequency Division Multiplexing (OFDM) and Interleave Division Multiple Access (IDMA) has been considered as an efficient technique due to its bandwidth efficiency, and robustness against MAI and ISI. Moreover, OFDM-IDMA technique has the ability to allow frequency diversity and performance improvement with the help of efficient FEC coding technique such as Low Density Parity Check (LDPC) code. Therefore, this paper addresses the performance of LDPC-coded-IDMA-based OFDM-UWB communication system under Gaussian and non-Gaussian noisy channels. Three different models as Symmetric Alpha Stable (SS), Laplacian model and Gaussian Mixture Model (GMM), have been introduced for approximating the non-Gaussian noise which are more realistic for UWB system. Simulation results show that LDPC-coded OFDM-IDMA system is robust against noise and interferences in UWB indoor environment, and achieves good performance under Cauchy (SS) model rather than other non-Gaussian models with simple Chip-By-Chip (CBC) iterative receiver. Furthermore, the proposed system gains a significant performance improvement compared with the un-coded OFDM-IDMA-UWB system under the studied noise models.

On the Design of Punctured Low Density Parity Check Codes for Variable Rate Systems

The authors face the problem of designing good LDPC codes for applications requiring variable, that is adaptive, rates. More precisely, the object of the paper is twofold. On one hand, we propose a deterministic (not random) procedureto construct good LDPC codes without constraints on the code dimension and rate. The method is based on the analysis and optimization of the local cycles length in the Tanner graph and gives the designer the chance to control complexity of the designed codes. On the other hand, we present a novel puncturing strategy which acts directly on the parity check matrix of the code, starting from the lowest rate needed, in order to allow the design of higher rate codes avoiding additional complexity of the co/decoding hardware. The efficiency of the proposed solution is tested through a number of numerical simulations. In particular, the puncturing strategy is applied for designing codes with rate variable between 0.715 and 0.906. The designed codes are used in conjunction with M-QAM constellations through a pragmatic approach that, however, yields very promising results.

Low Density Parity Check Code for OFDM Transmission Using Bit Flipping and Sum Product Algorithm

Low Density Parity Check Code for OFDM Transmission Using Bit Flipping and Sum Product Algorithm

CDF-LDPC

The raw error rate of a Solid-State drive (SSD) increases gradually with the increase of Program/Erase (P/E) cycles, retention time, and read cycles. Traditional approaches often use Error Correction Code (ECC) to ensure the reliability of SSDs. For error-free flash memory pages, time costs spent on ECC are redundant and make read performance suboptimal. This article presents a CRC-Detect-First LDPC (CDF-LDPC) algorithm to optimize the read performance of SSDs. The basic idea is to bypass Low-Density Parity-Check (LDPC) decoding of error-free flash memory pages, which can be found using a Cyclic Redundancy Check (CRC) code. Thus, error-free pages can be read directly without sacrificing the reliability of SSDs. Experiment results show that the read performance is improved more than 50% compared with traditional approaches. In particular, when idle time of benchmarks and SSD parallelism are exploited, CDF-LDPC can be performed more efficiently. In this case, the read performance of SSDs can be improved up to about 80% compared to that of the state-of-art.

Low Rank Parity Check Codes and their application in Power Line Communications smart grid networks

SummaryWe investigate the use of Low Rank Parity Check Codes, originally designed for cryptography applications in the context of Power Line Communication. Particularly, we propose a new code design and an efficient probabilistic decoding algorithm. The main idea of decoding Low Rank Parity Check Codes is based on calculations of vector spaces over a finite field . Low Rank Parity Check Codes can be seen as the identical of Low Density Parity check codes. We compare the performance of this code against the Reed‐Solomon Code through a Power Line Communication channel.

Data Storage and Retrieval on Nanoparticles

Recent advances at developing nanoscale electronic devices lead us to believe that in the near term the nanomemories in the form of nanodisks and nanotubes will replace existing storage systems and will be integrated into the implementation of nanocomputers and complex nanosensor systems. In this work the issue of recording and reading data using the magnetic vortex of nanodisks is addressed. By using the polarity and chirality properties of the magnetic vortex it may be possible to store information in binary or nonbinary form. Nevertheless, as in any storage system, information can be altered by the presence of noise, and therefore it is necessary to incorporate error control coding. In this regard, here we analyse the behaviour of the proposed system using Turbo coding and Low Density Parity Check (LDPC) coding in order to correct errors in the writing and reading process in nanoparticles. Simulations were performed for the binary case considering the polarity of the magnetic vortex to store information. This, because it appears to be the first workable level in the short term, before reaching practical implementations involving the simultaneous control of polarity and chirality to store non-binary data.