Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm

Sandeep Kakde,Atish Khobragade,Pranay Nandanwar,Shrikant Ambatkar

doi:10.31436/iiumej.v18i2.677

Sandeep Kakde, Atish Khobragade + Show 2 more

Open Access

https://doi.org/10.31436/iiumej.v18i2.677

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Abstract

For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives high throughput. The proposed work has been implemented and tested on Xilinx Virtex 5 FPGA. The MATLAB result of LDPC decoder for low bit error rate (BER) gives bit error rate in the range of 10-1 to 10-3.5 at SNR=1 to 2 for 20 no of iterations. So it gives good bit error rate performance. The latency of the parallel design of LDPC decoder has also reduced. It has accomplished 141.22 MHz maximum frequency and throughput of 2.02 Gbps while consuming less area of the design.

Highlights

Low Density Parity Check codes (LDPC) have gained major attention because of their performance near to the Shannon limit and remarkable error correction capability
bit error rate (BER) against signal to noise ratio (SNR) performance of un-coded binary phase shift-keying (BPSK) and MinSum algorithm over an AWGN channel, as shown in Fig. 7, is simulated in MATLAB software and found that min-sum algorithm shows exceptional BER against SNR performance when compared with the un-coded BPSK
This work provides the concept of implementing the LDPC Decoder with a new Check-Node Unit using a Min-Sum algorithm

Summary

INTRODUCTION

Low Density Parity Check codes (LDPC) have gained major attention because of their performance near to the Shannon limit and remarkable error correction capability. The LDPC decoder‟s implementation requires a balance between factors such as error correction performance, decoding throughput, and the hardware complexity. Partial parallel architecture is the best suited because multiple processing units are provided that allows proper trade-off between the hardware complexity and the decoding throughput. Chen and Fossorier had given a performance comparison for different check updates [9,10] In their research they showed that the offset min-sum decoding algorithm with 5-bit quantization could achieve the same BER performance as that of floating point sum-product and Jacobian-based BCJR algorithm (named after its discoverers Bahl, Cocke, Jelinik, and Raviv) with less than 0.1 dB penalty in SNR). A different and multi rate block length high throughput architecture is proposed in the paper [15, 16]

MIN-SUM DECODING ALGORITHM

DECODER ARCHITECTURE AND OPERATION

MATLAB IMPLEMENTATION RESULTS

VERILOG HDL IMPLEMENTATION RESULTS

CONCLUSION