Check Codes Research Articles

Lowering Error Floor of Irregular LDPC Codes by CRC and OSD Algorithm

Irregular Low-Density Parity-Check (LDPC) codes generally achieve better performance than regular LDPC codes at low E b /N 0 values. They have, however, higher error floors than regular LDPC codes. With respect to the construction of the irregular LDPC code, it can achieve the trade-off between the performance degradation of low E b /N 0 region and lowering error floor. It is known that a decoding algorithm can achieve very good performance if it combines the Ordered Statistic Decoding (OSD) algorithm and the Log Likelihood Ratio-Belief Propagation (LLR-BP) decoding algorithm. Unfortunately, all the codewords obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. While we can not use the parity check equation of the LDPC code to stop the decoding process, the wrong codeword that satisfies the parity check equation raises the error floor. Once a codeword that satisfies the parity check equation is generated by the LLR-BP decoding algorithm, we regard that codeword as the final estimate and halt decoding; the OSD algorithm is not performed. In this paper, we propose a new encoding/decoding scheme to lower the error floor created by irregular LDPC codes. The proposed encoding scheme encodes information bits by Cyclic Redundancy Check (CRC) and LDPC code. The proposed decoding scheme, which consists of the LLR-BP decoding, CRC check, and OSD decoding, detects errors in the codewords obtained by the LLR-BP decoding algorithm and the OSD decoding algorithm using the parity check equations of LDPC codes and CRC. Computer simulations show that the proposed encoding/decoding scheme can lower the error floor of irregular LDPC codes.

Low Encoding Complexity Video Compression Based on Low-Density Parity Check Codes

Conventional video compression methods generally require a large amount of computation in the encoding process because they perform motion estimations. In order to reduce the encoding complexity for video compression, this paper proposes a new video compression method based on low-density parity check codes. The proposed method is suitable for resource-constrained devices such as mobile phones and satellite cameras.

Decoding Algorithms Based on Oscillation for Low-Density Parity Check Codes

In this paper we focus on the decoding error of the Log-Likelihood Ratio Belief Propagation (LLR-BP) decoding algorithm caused by oscillation. The decoding error caused by the oscillation is dominant in high b/N0 region. Oscillation of the LLR of the extrinsic value in the bit node process (ex-LLR) is propagated to the other bits and affects the whole decoding. The Ordered Statistic Decoding (OSD) algorithm is known to improve the error rate performance of the LLR-BP decoding algorithm. The OSD algorithm is performed by deciding the reliability of each bit based on a posteriori probability. In this paper we propose two decoding algorithms based on two types of oscillations of LLR for LDPC codes. One is the oscillation-based OSD algorithm with deciding the reliability of each bit based on oscillation. The other is the oscillation-based LLR-BP decoding algorithm that modifies ex-LLR based on oscillation. In the oscillation-based LLR-BP decoding algorithm, when ex-LLR oscillates, then we reduce the magnitude of this ex-LLR to reduce the effects on the other bits. Both algorithms improve the decoding errors caused by oscillation. From the computer simulations, we show that paying attention to the oscillation, we can improve the error rate performance of the LLR-BP decoding algorithm.

A Trellis-Based Method for Removing Cycles From Bipartite Graphs and Construction of Low Density Parity Check Codes

This letter presents a trellis-based iterative method for removing short cycles from bipartite graphs. This method can be used to improve the performance of low density parity check (LDPC) codes or to construct new LDPC codes.

Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes

In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.

Run-Length-Limited Low-Density Parity Check Codes Based on Deliberate Error Insertion

We propose a novel approach to modulation and error control coding. The idea is to completely eliminate a constrained encoder and, instead, impose the constraint by the deliberate introduction of bit errors before transmission. The redundancy that would have been used for imposing the constraint is used in our scheme to strengthen the error control code (ECC), in such a way that the ECC becomes capable of correcting both deliberate errors as well as channel errors that occur during the detection. Our ECC-modulation scheme is based on iterative decoding of low-density parity check codes and a run-length constraint.

Performance of Low Density Parity Check Codes as a Function of Actual and Assumed Noise Levels

We investigate how sensitive Gallager's codes are, when decoded by the sum-product algorithm, to the assumed noise level. We have found a remarkably simple function that fits the empirical results as a function of the actual noise level at both high and low noise levels.

Affine Geometry Low-density Parity Check Codes in Long-haul Optical Communications

Affine Geometry Low-density Parity Check Codes in Long-haul Optical Communications

Affine Geometry Low-density Parity Check Codes in Long-haul Optical Communications

In this paper we investigate the performance of low-density parity-check (LDPC) codes in long haul optical communication systems. We are particularly concerned with high-rate codes on affine geometries. These codes have large minimum distance and simple iterative decoding algorithm, which makes them good candidates for high-speed applications such as optical communications. We consider both the bit-flipping iterative decoding and iterative decoding based on min-sum algorithm. We demonstrate a significant performance improvement with respect to the state-of-the-art error control schemes employed in long-haul systems for different signal formats (NRZ, RZ, CRZ). Contrary to the common practice of considering the error controlling schemes using the AWGN channel assumption, we consider the performance of the proposed LDPC schemes taking into account in a natural way all major impairments in a long-haul optical transmission such as ASE noise, pulse distortion due to fiber nonlinearities, chromatic dispersion or polarization dispersion, crosstalk effects, intersymbol-interference, etc.

Low-Density Parity Check Code Concatenated with Generalized Partial Response Equalizer for High-Capacity Magneto-Optic Recording Channels

In this study, we investigate the application of advanced coding and signal processing techniques for a magneto-optical (MO) disk system in order to improve its recording capacity. In particular, we study the application of low-density parity check (LDPC) codes with iterative soft decoding to the center aperture detection magneto-optical (CAD-MO) recording channel. The channel pulse response is identified from the read-back signals using the least mean squares (LMS) algorithm. The minimum mean-squared error (MMSE) technique was used to design appropriate generalized partial response (GPR) targets. LDPC encoded data are written onto and digitized read back signals are collected from a spin stand. Off-line numerical evaluations show that LDPC code concatenated with a channel detector matched to the GPR target can increase the capacity.

Iteratively Decodable Block Codes for Long Haul Optical Transmission Systems

A Forward Error Correction (FEC) scheme based on Low Density Parity Check (LDPC) codes, constructed using mutually orthogonal Latin rectangles, is presented in this paper. We show that LDPC codes provide a significant system performance improvement with respect to the state-of-the-art FEC schemes employed in optical communications systems.

VLSI architectures for iterative decoders in magnetic recording channels

VLST implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response maximum likelihood (PRML) systems, at the expense of increased complexity. This paper analyzes the requirements for computational hardware and memory, and provides suggestions for reduced-complexity decoding and reduced control logic. Serial concatenation of interleaved codes, using an outer block code with a partial response channel acting as an inner encoder, is of special interest for magnetic storage applications.

Area efficient architectures for information integrity in cache memories

Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data integrity and the chip area requirement. We focus on transient fault tolerance in primary cache memories and develop new architectural solutions, to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. The underlying idea is to exploit the corollary of reference locality in the organization and management of the code. A higher protection priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher probability of access. The error-prone likelihood prediction is based on the access frequency. We evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined with software error injection using four different fault manifestation models. From the simulation results, we show that for most benchmarks the proposed architectures are effective and area efficient for increasing the cache integrity under all four models.

Efficient computation of packet CRC from partial CRCs with application to the Cells-In-Frames protocol

A Cyclic Redundancy Check (CRC) code is used by many communications protocols for packet error detection. Computation of CRC for an entire packet is easily implemented in hardware if packets are transmitted and received in contiguous form. In an ATM network, packets are fragmented into cells and, in the case of multiple virtual circuits, their transmission is overlapped, resulting in non-contiguous packets. For non-contiguous packets with a 32-bit CRC (CRC-32), as in the case of ATM Adaptation Layer 5 (AAL5), an efficient algorithm for computing the CRC for an entire packet based on combining packet fragment CRCs (e.g., cell CRCs) is developed in this paper. In this algorithm, the network hardware generates cell or partial packet CRCs and the host system software combines these CRCs into a full packet CRC. Several important properties for CRCs are described and proved, and the correctness of the algorithm developed from these properties is then also formally proved. The algorithm has direct application to the proposed Cells-In-Frames (CIF) architecture for support of ATM AAL5 services on Ethernet. When implemented in software, the algorithm is shown to be significantly faster than a table-based software computation of packet CRC-32. The algorithm is also applicable to networking devices that need to change the contents of a packet and quickly recompute the packet CRC based only on the changed portions of the packet.

Getting familiar with map in the process industries

Even Parity? Old Parity? Polynomial Checksum? Vertical Byte Parity? BCH Check Code? Cyclical Redundancy Check Code? These are just some of the communication formats currently being used to send information between computers within a network. Whenever a supplier provides a system, a “proprietary” or peculiar protocol is established to operate between the elements of the network. When it is desired to interconnect digital equipment of two or more suppliers, a “custom” interface is required. As long as the two suppliers do not revise their native codes, the custom interface can be reproduced for another application. MAP is a standardized communication format intended to eliminate the wide variety of proprietary formats and the need for custom interfaces between different suppliers of digital equipment and systems. Thus, the term “open” systems interconnect (OSI) and interoperability have been popularized to represent this emerging technology.

Redundancy Check Code (RCC): a New Error Protection Scheme for Digital Image Recording Applications

A new family of error correction codes for digital image recording applications, generally termed Redundancy Check Code (RCC), is 4escribed in this paper. Both the fundamentals and related system design considerations of the RCC are discussed extensively. Experimental results using the MAXMIN algorithm on recorded images from a multi-channel digital magnetic recording system are presented.

Parity Check Codes for Logic Processors

Parity Check Codes for Logic Processors

Augmented Parity Check Codes for Encoding of Asynchronous Sequential Machines

Critical races can be avoided in the binary encoding of asynchronous sequential machines by making use of general codes employing-multistep changes in secondary variables to accomplish transitions between states. The shortest length code of this type presently available is Huffman's internmeshed row set code, which encodes race-free any 2SO-row flow table with 2S o -1 bits. In this paper, a new class of codes called augmented parity check codes (APC codes) is introduced and proposed for race-free encoding. Some of the properties of these codes suggest that minimum codes may require only on the order of S o + log 2 S O bits.