Charge Pumping Method Research Articles

An experimental comparison of interface trap density in hafnium oxide-based FeFETs

In recent years, there has been significant progress in the development of high-κ materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-κ FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.

Charge pumping electrically detected magnetic resonance of silicon carbide power transistors

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 1013−1017 cm−2. We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields.

Importance of temperature dependence of interface traps in high-k metal gate stacks for silicon spin-qubit development

While semiconductor-based spin qubits have demonstrated promising fidelities exceeding 99.9%, their coherence time is limited by the presence of charge noise. However, fast process optimization for reduced charge noise becomes challenging due to the time-consuming nature of cryogenic measurements. Hence, this work explores low frequency analysis methods to determine interface trap densities, their temperature dependence, and correlation with observed noise levels. The herein presented results provide evidence for strong temperature dependence of the interface trap density. Moreover, good agreement is observed between charge pumping and conductance-based methods. Finally, differences in temperature dependent trends of flicker noise are observed, indicating additional influences, which need to be considered for further device optimization.

Investigations on 4H-SiC Low Voltage nMOSFETs with Thin Thermal SiO<sub>2</sub>/ Deposited Oxide Gate Dielectric

The poor quality of SiC/SiO2 interface significantly limits the channel mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation by NO has been adopted widely by manufactures because nitrogen may replace carbon in some chemical bond at the SiC/SiO2 interface. However, excessive nitridation is not desirable because of pronounced hole-trapping effects near the conduction band. As an alternative gate dielectric, thin SiO2/deposited oxide stack has been investigated in 4H-SiC lateral nMOSFETs. Overall performances were reviewed in aspects of transfer/gm/reverse characteristics, charge pumping method and TLP characteristics.

Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor

We propose a hybrid self-curing method based on the parasitic bipolar junction transistor (PBJT) inherent to metal-oxide-semiconductor field-effect transistor (MOSFET). The PBJT utilizes the positive feedback of impact ionization to flow a large current close to the channel, generating Joule heat. Unlike conventional self-curing methods, the PBJT-based self-curing recovers the damaged gate oxide along the lateral dimension of the entire channel. The effects of the hybrid curing are quantitatively verified by low-frequency noise spectroscopy and charge pumping method.

Interface traps density extraction through transient measurements in junctionless transistors

This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Defect characterization in floating body transistors using a single pulse charge pumping method

Field-effect transistors on a floating body channel have been used for a range of applications, such as three-dimensional nand flash and high-performance devices on silicon-on-insulator wafers. Conventional techniques to characterize the defect states cannot be implemented because those transistors do not have body contacts. A single-pulse charge pumping (SPCP) method was introduced to characterize the defect state distribution of the floating body transistors. The results extracted from the SPCP method on the three-terminal transistors (without body contact) agreed well with those from a conventional charge pumping method or SPCP on four-terminal transistors (with body contact). The validity of the SPCP measurement of the floating body devices was demonstrated by monitoring the increase in the defect state of the three-terminal poly-Si transistors density during the bias stress test. The SPCP method could detect the defect states of floating body transistors with high resolution.

Topology of non-inductive DC/DC converters with galvanic isolated circuits

Non-inductive (throttle-free) DC/DC converters are used in low-power and highly integrated electronic systems. A circuit analysis of the basic topologies of non-inductive DC/DC charge-pumped converters which perform typical DC-voltage conversions, i.e., lowering, raising and inverting, was carried out. The galvanic isolation between the input and output circuits of the converter was achieved even in the integrated version due to forming a time delay of the switches (Dead Time, DT), commuting a “flying” capacitor, which is transferring the charge to the storage capacitor and the load. A circuit of the DT driver was developed and its parameters, at which the through-current flow in the switch is prevented and the conditions of galvanic isolation of the input and output circuits are satisfied, were studied. The simulation was built with a popular Electronics Workbench software, widely used in training of specialists in radio electronics at higher educational institutions. The results of the study of the basic power characteristics of DC/DC conversion, such as output current and voltage, voltage transfer coefficient, efficiency, output equivalent resistance, were presented. The efficiency of conversion was estimated by varying the capacities of the “flying” and storage capacitors, the resistance of the switches in the closed state, and the frequency of switching. It is proved that the charge pumping method is simple and effective at low load currents (mA units), when both the voltage transfer coefficient from input to output and efficiency are high, and are approaching to “one”. However, with the increase of the load current, the voltage transfer coefficient and efficiency decrease, the output voltage ripples increase.

Localizing Hot-Carrier Degradation in Silicon Trench MOSFETs

Hot-carrier degradation (HCD) is investigated in silicon trench MOSFETs with field plate compensation. With the aid of charge pumping (CP), it is possible to obtain the total trap densities created by the hot-carrier stress. We will demonstrate that, in combination with TCAD simulations, profiling of the spatial distribution of the damage at the interface is possible in the accessible regions by extending the well-known reverse-bias CP method for planar devices to trench devices. Four process variations are investigated to show the impact of the cell geometry on the degradation location with the results being confirmed by capacitance measurements. It is found that the impact ionization rate seen in drift-diffusion TCAD simulations provides a straightforward means to estimate the defect locations.

Effect of PECVD Gate SiO2 Thickness on the Poly-Si/SiO2 Interface in Low-Temperature Polycrystalline Silicon TFTs

This study investigates the effect of the gate SiO2 thickness (80, 100, and 130 nm) deposited by plasma enhanced chemical vapor deposition on the interface and reliability characteristics of low-temperature polycrystalline silicon thin film transistors. Field effect mobility is significantly degraded as the gate oxide thickness decreases. The border trap density (Nbt) extracted from capacitance–voltage hysteresis exhibits no trend with respect to the gate oxide thickness, indicating that field effect mobility is not governed by Nbt. The quantitative interface trap density (Nit) was obtained using a 3-terminal charge pumping method; results showed that Nit decreased as the gate oxide thickness increased. However, it was observed that the threshold voltage (Vth) shift during negative bias temperature stress is worse in the thicker SiO2 film, which has a low Nit. After activation annealing, the amount of hydrogen in the gate oxide increased as the thickness of the insulator was raised. This in turn caused a larger shift in Vth. To validate this mechanism, the amount of hydrogen with respect to the device depth was analyzed via secondary ion mass spectroscopy. It has been found that the presence of more hydrogen concentration in the SiO2 film and the interface to the thicker SiO2 results in more Vth shifts under bias temperature stress.

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

Investigation of the Temperature Dependence of Hot-Carrier Degradation in Si MOSFETs Using Spectroscopic Charge Pumping

The temperature dependence of defect generation due to hot-carrier stress (HCS) is investigated in long-channel nMOSFETs with a SiO2 insulator. In order to improve the understanding of hot-carrier degradation, we systematically investigate the impact of temperature on the HCS-induced trap densities and their energetic profiles using standard and spectroscopic charge pumping (CP). With the aid of polyheaters, which can rapidly change the device temperature, recovery of the degradation at higher temperatures is minimized by quickly switching the temperature to the characterization temperature of −60 °C. In order to be able to quantitatively analyze the trap profiles measured with spectroscopic CP, a method for finding the correct capture cross section is suggested. Both CP methods yield comparable results, and it is shown that the same types of defects are created at all temperatures. In agreement with the literature, lower stress temperatures during HCS result in the creation of a larger number of defects for our long-channel devices.

Lateral Profiling of Defects and Charges in Oxide Semiconductor Channel Thin-Film Transistors

The lateral distributions of free carriers and defects in a channel of top gate In-Ga-Zn-O thin-film transistors were extracted using a single pulse charge pumping method. A square pulse was applied to the gate, while the charge transport current was monitored at the source–drain. A transmission line model was used to confirm the charging mechanism and extract the effective charge length. The time dependence of the trapped charge density was determined by comparing the charging and discharging transient characteristics. The lateral profiles of the free carriers and defects were decoupled successfully using the time dependence of the effective charge length, free charges, and trapped charges.

Ultrafast Pulsed <i>I-V</i> and Charge Pumping Interface Characterization of Low-Voltage <i>n</i>-Channel SiC MOSFETs

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects, defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

Influence of Self-Heating Effect on Interface Trap Generation in Highly Flexible Single-Crystalline Si Nanomembrane Transistors.

We analyze the interface trap states generated by the self-heating effect in flexible single-crystalline Si nanomembrane (sc-Si NM) transistors. Despite the excellent device performance (Subthreshold swing: ~61 mV/dec, Ion/off: ~109, Nit: ~5 × 1010 cm-2, µeff: ~250 cm²/V·s) and mechanical flexibility (RB,min ═ 1 mm) of sc-Si NM transistors on a polymer substrate, they are vulnerable to thermal reliability issues due to the poor thermal conductivity (κ < 1 W/m·K) of the polymer substrate. Understanding the detailed mechanism driving heat-related device degradation is key to improving device reliability, life expectancy, and overall device performance. Thus, a charge pumping method was employed to systematically analyze the device degradation caused by the self-heating effect. This enabled the interface trap density to be investigated for the flexible sc-Si NM transistors on a polymer substrate after a bias stress. For comparison, a heat spreading layer (HSL) made using a 1-µm thick Ag film (κ~400 W/m·K) was integrated into the sc-Si NM device to mitigate the self-heating effect. The results showed that the interface trap density was proportional to the self-heating effect. This facilitated the fundamental understanding of the self-heating effect of flexible sc-Si NM transistors, opening a robust route to realizing high performance flexible devices using sc-Si NM.

Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

A thorough investigation of trap density (Dit) in defective zones of Tunnel FET (TFET) devices is presented. The TFETs were fabricated with standard high-temperature (HT, 1050ºC) and low-temperature (LT, 600ºC) processes [1]. A larger average of defects at the top surface in LT process TFETs was found [2]. For the first time, we use charge pumping (CP) method [3] in Silicon On Insulator (SOI) HT & LT TFETs (Fig. 1) with a ultrathin silicon thickness of 11 nm, EOT of 1.18 nm and 145 nm thick BOX [4]. CP method requires the presence of majority and minority carriers since ICP current results from the recombination of detrapped electrons in the channel region with holes. Therefore, ICP is proportional to Dit and frequency. In FDSOI structures, the top and bottom interfaces are extremely close. This means that the pulse applied on the front-gate can sweep the whole film from accumulation to inversion. Carriers from the top region could also be trapped in defects located at the back interface, enabling a net contribution to the ICP current and thus, providing a non-accurate value of Dit. For this reason, it is mandatory to apply a back-gate voltage (VBG) in order to avoid the scanning of the back interface traps. In the past, the influence of the substrate polarization on the CP current has been studied for SOI devices with thicker films (from 450 nm to 100 nm) [5,6,7]. Here, we present the relation between the CP current (experiments) and the carrier concentration (TCAD simulation), for TFETs with ultrathin film. Specifically, for VBG = -20V at VG,top = +0.65V the electron density is located at the top surface, while the back interface is depleted of electrons (lower than 1015 cm-3). For VG,base = -0.65V, two layers of holes are formed at the channel interfaces. Considering both mechanisms at the same time, during the falling edge of the pulse, the concentration of electrons that could be trapped by defects at the bottom interface is at best equal to 1015 cm-3. Although the concentration of holes is significantly higher, the recombination at the back-interface is negligible because it is proportional to the lowest concentration of either carriers (here electrons). So, traps at the back-interface are rather empty of electrons and their contribution to ICP is low. The situation is different for VBG = +20V: at VG,top = +0.65V, electrons are present at each interface. At VG,base = -0.65V, the hole density is only formed at the top surface, while the back-interface is depleted of holes, deactivating the possibility of recombination. Finally, when VBG = 0V, electron and hole concentrations at the back-interface are more similar and participate in the recombination process. Simulation results indicate that the variation of the ICP depends of the carriers available for recombination at the front and back interfaces. Therefore either one of these concentrations decreases when the back-gate voltage is more negative (fewer electrons) or more positive (fewer holes), not only at the back but also at the top interface. Fig. 2 shows the minority carrier concentration (which governs the recombination rate and ICP) for different applied back-gate voltages. The curve of the carrier concentration presents the same shape as the one obtained for the experimental charge pumping current [2], explaining the recombination mechanism. Same consistent results between experiments and simulations have been obtained for different VG,base voltages respectively (-0.35 V and -0.85 V). We discuss in detail the shape of CP curves as well as the back-gate selection for the traps at the back-interface to have negligible contribution to the front-pulse CP current. Our updated CP method is applied to determine and compare the density of traps in HT and LT FD-SOI TFETs. Acknowledgments This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11. References C. Le Royer et al, EuroSoi-Ulis, pp. 69-72, (2015).C. D. Llorente et al, IEEE S3S, (2018).J. S. Brugler and P.G.A. Jespers, IEEE TED., vol. 16, no. 3 (1969).C. D. Llorente et al, Solid-State Electron., vol.144, pp.78-85 (2018).T. Ouisse et al, Trans. Electron Devices., vol.38, no.6 (1991).D. J. Wouters et al, Trans. Electron Devices, vol.36, no.9 (1989).Y. Li and T. P. Ma, Trans. Electron Devices, vol.45, no.6 (1998). Figure 1

Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

A thorough investigation of trap density (Dit ) at the interfaces of FD-SOI Tunnel FET (TFET) devices is presented. Charge pumping (CP) method confirms a larger average defect concentration at the top interface of Low-Temperature processed TFETs than in devices made using a standard high-temperature process. Back-gate bias is used to avoid probing the back-interface traps. We demonstrate the link between the CP current (experiments) and the carrier concentration (TCAD) at the interfaces during measurement. Simulation results demonstrate that the unusual variation of CP current in ultrathin FD-SOI depends on the carriers available for recombination at both front and back interfaces.

Charge Pumping of Low-Voltage Silicon Trench Powers MOSFETs

Interface- and border-traps at the Si-SiO2 interface are investigated in trench power MOSFETs. We show that the popular charge pumping method is not limited to conventional lateral devices but can also be applied to these more complex structures. A new approach for the localization of defects is presented, using devices with two or more differently doped areas adjacent to the Si-SiO2 interface. Based on those doping profile variations, different areas of the interface can be assigned to particular intervals of the measured charge pumping signal. By varying the geometrical aspect ratios and the areas of the investigated devices, we demonstrate that the interface- and border-trap density on the edges of the structures is significantly higher than in the active area. Finally, challenges arising in the measurement setup are discussed.