Abstract
A thorough investigation of trap density (Dit ) at the interfaces of FD-SOI Tunnel FET (TFET) devices is presented. Charge pumping (CP) method confirms a larger average defect concentration at the top interface of Low-Temperature processed TFETs than in devices made using a standard high-temperature process. Back-gate bias is used to avoid probing the back-interface traps. We demonstrate the link between the CP current (experiments) and the carrier concentration (TCAD) at the interfaces during measurement. Simulation results demonstrate that the unusual variation of CP current in ultrathin FD-SOI depends on the carriers available for recombination at both front and back interfaces.
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