Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

Abstract

A thorough investigation of trap density (Dit) in defective zones of Tunnel FET (TFET) devices is presented. The TFETs were fabricated with standard high-temperature (HT, 1050ºC) and low-temperature (LT, 600ºC) processes [1]. A larger average of defects at the top surface in LT process TFETs was found [2]. For the first time, we use charge pumping (CP) method [3] in Silicon On Insulator (SOI) HT & LT TFETs (Fig. 1) with a ultrathin silicon thickness of 11 nm, EOT of 1.18 nm and 145 nm thick BOX [4]. CP method requires the presence of majority and minority carriers since ICP current results from the recombination of detrapped electrons in the channel region with holes. Therefore, ICP is proportional to Dit and frequency. In FDSOI structures, the top and bottom interfaces are extremely close. This means that the pulse applied on the front-gate can sweep the whole film from accumulation to inversion. Carriers from the top region could also be trapped in defects located at the back interface, enabling a net contribution to the ICP current and thus, providing a non-accurate value of Dit. For this reason, it is mandatory to apply a back-gate voltage (VBG) in order to avoid the scanning of the back interface traps. In the past, the influence of the substrate polarization on the CP current has been studied for SOI devices with thicker films (from 450 nm to 100 nm) [5,6,7]. Here, we present the relation between the CP current (experiments) and the carrier concentration (TCAD simulation), for TFETs with ultrathin film. Specifically, for VBG = -20V at VG,top = +0.65V the electron density is located at the top surface, while the back interface is depleted of electrons (lower than 1015 cm-3). For VG,base = -0.65V, two layers of holes are formed at the channel interfaces. Considering both mechanisms at the same time, during the falling edge of the pulse, the concentration of electrons that could be trapped by defects at the bottom interface is at best equal to 1015 cm-3. Although the concentration of holes is significantly higher, the recombination at the back-interface is negligible because it is proportional to the lowest concentration of either carriers (here electrons). So, traps at the back-interface are rather empty of electrons and their contribution to ICP is low. The situation is different for VBG = +20V: at VG,top = +0.65V, electrons are present at each interface. At VG,base = -0.65V, the hole density is only formed at the top surface, while the back-interface is depleted of holes, deactivating the possibility of recombination. Finally, when VBG = 0V, electron and hole concentrations at the back-interface are more similar and participate in the recombination process. Simulation results indicate that the variation of the ICP depends of the carriers available for recombination at the front and back interfaces. Therefore either one of these concentrations decreases when the back-gate voltage is more negative (fewer electrons) or more positive (fewer holes), not only at the back but also at the top interface. Fig. 2 shows the minority carrier concentration (which governs the recombination rate and ICP) for different applied back-gate voltages. The curve of the carrier concentration presents the same shape as the one obtained for the experimental charge pumping current [2], explaining the recombination mechanism. Same consistent results between experiments and simulations have been obtained for different VG,base voltages respectively (-0.35 V and -0.85 V). We discuss in detail the shape of CP curves as well as the back-gate selection for the traps at the back-interface to have negligible contribution to the front-pulse CP current. Our updated CP method is applied to determine and compare the density of traps in HT and LT FD-SOI TFETs. Acknowledgments This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11. References C. Le Royer et al, EuroSoi-Ulis, pp. 69-72, (2015).C. D. Llorente et al, IEEE S3S, (2018).J. S. Brugler and P.G.A. Jespers, IEEE TED., vol. 16, no. 3 (1969).C. D. Llorente et al, Solid-State Electron., vol.144, pp.78-85 (2018).T. Ouisse et al, Trans. Electron Devices., vol.38, no.6 (1991).D. J. Wouters et al, Trans. Electron Devices, vol.36, no.9 (1989).Y. Li and T. P. Ma, Trans. Electron Devices, vol.45, no.6 (1998). Figure 1