Charge Pumping Method Research Articles

Why Is Oxide-Trap Charge-Pumping Method Appropriate for Radiation-Induced Trap Depiction in MOSFET?

Radiation-induced traps, which are generally identified using specific extraction methods, play an important role in the reliability of MOS devices. In this paper, the oxide-trap-based-on-charge-pumping (OTCP) method is used to estimate radiation-induced oxide, interface, and border traps in complementary N- and P-MOS transistors. We emphasize on the critical comparison between the OTCP and classical methods like subthreshold slope (STS), midgap (MG), capacitance-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> ), dual-transistor CP (DTCP), and DT border trap (DTBT), giving a clear insight on the benefits and limitations of OTCP. According to experimental data, the OTCP method is often more accurate than the classical methods. On one side, OTCP offers more accurate densities of radiation-induced interface traps (Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) and border traps (Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bt</sub> ), while STS and MG overestimate Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> because both interface and border traps are sensed like interface traps. On the other side, OTCP estimates Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> , Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bt</sub> , and oxide trap (Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) for N- and P-MOSFETs separately, while DTCP and DTBT give average densities for whole N- and P-MOS devices. Finally, Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> obtained by OTCP is in excellent agreement with that given by <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> . However, they show a slight discrepancy in the Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> extraction.

Advanced Analysis of Silicon Insulator Interface Traps in MOSFET's with SiO2 and HfO2 as Gate Dielectrics

In this paper and using the charge pumping method, it is shown that in state-of-the-art fully processed MOSFET's the Si-SiO2 interface traps have the same properties as those of the Pb0 center. The question as to whether these defects are Pb0 centers is discussed. Devices using HfO2 as gate dielectric are also studied. In spite of some differences, it is found that the traps at the Si-SiO2 interface in these devices have the same properties as those in state-of-the-art fully processed MOSFET's. These differences are discussed. Finally, a method for extracting the interface trap density from the slope of the charge pumping curves is proposed and applied to the two kinds of devices studied.

New Insights of BTI Degradation in MOSFETs with SiON Gate Dielectrics

It is widely recognized that recovery during measurement delay seriously misleads the BTI phenomena. We have developed a modified Charge Pumping (MCP) method to measure the interface trap generation under stress with negligible recovery during measurement delay. The method simply extends the inversion level Vinv of the CP pulse to the stress voltage and keeps the duty cycle of Vinv as large as possible, therefore the stress is almost "on" during measurement. For the first time, we developed a diagram representation of CP process and used to the physical analysis for the contribution and exclusion of slow oxide charge contribution in the CP current of this MCP method. Using this MCP method and the fast pulsed Id-Vg method (FPM) we developed in the past, we systematically investigate and compare the NBTI degradation of p-MOSFETs with thermal (TNO) and plasma (PNO) nitrided SiON gate dielectrics with the same nitrogen surface concentration. We also systematically measure the interface trap degradations in four configurations of NBTI and PBTI stresses for both n-MOSFETs and p-MOSFETs. The following results are achieved: (1) The oxide charge induced degradation in TNO SiON devices is several times larger than those in PNO devices under the same stress condition, due to the larger charge moment in the gate dielectrics of the TNO devices. (2)

Optical Charge Pumping Method for Extracting the Energy Level of Interface States in a Program/Erase Cycled SONOS Flash Memory Cell and Its Program Time Dependence

Optical Charge Pumping Method for Extracting the Energy Level of Interface States in a Program/Erase Cycled SONOS Flash Memory Cell and Its Program Time Dependence Kichan Jeon, Sunyeong Lee, Jun-Hyun Park, Changmin Choi, Kwan-Jae Song, So Ra Park, Tae Woon Kim, Ji Eun Lee, Sungwook Park, Sangwon Lee, Jaeman Jang, Dae Hwan Kim and Dong Myong Kim School of Electrical Engineering, Kookmin University, Seoul 136-702 (Received 20 February 2008) The optical charge pumping (CP) technique is proposed as a simple and fast method for extracting the energy distribution of the interface trap, Dit, of silicon-oxide-nitride-oxide-silicon (SONOS) ash memories. It is based on the subthreshold slope change induced by optically excited traps and interface states in SONOS memory cell transistors under sub-bandgap photonic illumination. This technique is advantageous for characterizing charge traps in nano-scale emerging devices. The technique has been applied to SONOS charge-trapping ash memories and the generation and the passivation of interface traps are investigated as a function of both the number of program/erase cycles and the program time. PACS numbers: 85.30.De, 85.30.Tv

Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications

The interface states have been one of the main reliability concerns for nano-scale metal oxide semiconductor field effect transistors (MOSFETs). Especially, the stress induced interface states generation is very important. For quantitatively clarify, the high-frequency charge pumping technique is presented and it has better accuracy and easier than former charge pumping method, which needs variable rise and fall times of gate pulse. Furthermore, it can reject border traps effect. Using the presented method, the energy distribution of interface states was extracted and the Fowler–Nordheim stress induced energy level of interface states was profiled in pure silicon dioxide and finely engineered remote plasma nitrided oxide. The technique is well suited for investigating the nano-scale MOSFET reliabilities.

Extraction of Energy Distribution of Nitride Traps Using Charge Pumping Method in Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

A new charge pumping method is developed and applied to extract the energy distribution of nitride traps in silicon–oxide–nitride–oxide–silicon (SONOS) flash memory. Based on the Frenkel–Poole emission model and the tunneling probability given by Wentzel–Kramers–Brillouin (WKB) approximation, we proposed an advanced model of charge pumping current for SONOS device having thick tunnel oxide (>3 nm). The detection range of trap energy depth in our experiment conditions is 1.06–1.24 eV. The extracted trap density distribution in energy levels of the nitride layer of prepared sample shows the peak trap density of 1.21 ×1020 eV-1 cm-3 at 1.17 eV while the peak trap density extracted using retention model is 6.24 ×1019 eV-1 cm-3 at 1.32 eV. This difference of the peak trap density and energy level at the peak trap density is originated from different tunneling probability of tunnel oxide during the measurement.

A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs

A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence ( ~ t n) of interface-trap generation is observed. The index n is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.

Trapped Electron and Hole Distribution Mismatch Induced Reliability Degradation of SONOS Type Memory Devices

The reliability of silicon-oxide-nitride-oxide-silicon (SONOS) type memories was analyzed using the charge pumping method and I-V tests at different temperatures to study its endurance and retention characteristics. A simple model was used to explain the charge loss phenomenon, with a dual-erasure method developed to improve the endurance and retention characteristics. The results indicate that the coexistence of injected holes and electrons after long term cycling, referred to as the mismatch problem, leads to degradation of the device characteristics. With the dual-erasure method, the threshold voltage, V T, window is maintained after 1×10 4 programming and erasing cycles and the charge loss is reduced by 410 mV after 72 h baking at 120°C.

Interface-Engineered High-Mobility High-$k$/Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) of 2 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ldr eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for Ge MOS capacitors. A hole mobility up to 396 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> plusmn 1 V. A high drain current of 37.8 muA/mum at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.

Applicability of Charge Pumping on Germanium MOSFETs

In this letter, the charge-pumping (CP) technique is validated for germanium MOSFETs. Effects of the smaller Ge bandgap on CP are discussed through both experiments and simulations. The standard CP setup with ~ 100-ns transition times at room temperature tuned for Si/SiO2 MOS evaluates the Ge interface-trap density only near midgap, and the total density is thus strongly underestimated. We show two CP methods which can be used to correctly reflect the actual complete interface-trap density by probing closer to the band edges. The use of low-temperature measurements to probe traps near the band edges with CP is discussed. CP measurements are demonstrated with transition times down to 6-ns at 300-K without making use of RF structures. Using these fast measurements, it is possible to obtain an interface state density closer to the band edges for Ge MOSFETs at 300-K.

Achieving a low interfacial density of states in atomic layer deposited Al2O3 on In0.53Ga0.47As

Atomic-layer-deposited Al2O3 on In0.53Ga0.47As with short air exposure between the oxide and semiconductor deposition has enabled the demonstration of nearly ideal frequency-dependent and quasistatic capacitance-voltage (C-V) characteristics. The excellent quasistatic C-V characteristics indicate a high efficiency of 63% for the Fermi-level movement near the midgap. A low mean interfacial density of states (D¯it)∼2.5×1011 cm−2 eV−1 was determined under 1 MHz using a charge pumping method, which was also employed to probe the depth profile of bulk traps (Nbt) and the energy dependence of Dit at 50 kHz: a low Nbt∼7×1018 cm−3 and a Dit of (2–4)×1011 cm−2 eV−1 in the lower half of the band gap and a higher Dit of ∼1012 cm−2 eV−1 in the upper half of the band gap. The employment of charge pumping method has given a more accurate determination of Dit, which is usually overestimated using other commonly methods such as the Terman, conductance, and high-low frequencies due to the influence of weak inversion at room temperature.

Energy distribution of interface traps in germanium metal-oxide-semiconductor field effect transistors with HfO2 gate dielectric and its impact on mobility

The energy distribution of interface trap density (Dit) in HfO2 gated germanium metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated by using charge pumping method with variable rise/fall-time measurement. Our results reveal that a high density of interface traps is present in the upper half of the Ge bandgap. As a result, the inversion-layer electron mobility of Ge n-channel MOSFETs was significantly degraded by the Coulomb scatterings. These results are also consistent with the abnormal capacitance-voltage (C-V) characteristics of Ge MOS capacitors.

Observation of Reliability of HfZrOX Gate Dielectric Devices with Different Zr/Hf Ratios

The impact of the Zr/Hf ratio on the reliability of a HfZrOX gate dielectric has been investigated in detail. By a frequency-varied charge-pumping method, we found that the density of bulk traps is reduced with increasing Zr content. Also, a comparable Dit value observed by the rising/falling time-varied charge-pumping method suggests that Zr incorporation does not degrade the interface quality. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ∼25% mobility enhancement compared with that of HfO2 can be observed. However, the bulk trap density reduction reaches saturation at a higher Zr content. The improvement in positive-bias temperature instability (PBTI) was also demonstrated by both DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. Finally, a reduced gate-induced drain leakage current (GIDL) was also observed with increasing Zr content because of the reduction of trap-assisted tunneling in a high-k film.

New Charge Pumping Method for Characterization of Charge Trapping Layer in Oxide–Nitride–Oxide Structure

Ramping amplitude multi-frequency charge pumping technique is proposed to analyze the nitride traps in silicon–oxide–nitride–oxide–silicon (SONOS) structure. Based on the method, the trap density and the capture cross section at each location in oxide–nitride–oxide (ONO) gate stack can be extracted separately. The trap parameters extracted from the suggested model show that the traps located at tunnel-oxide/nitride interface whose capture cross section is lowest. The cause of large trap density at tunnel-oxide/nitride interface may be due to Si–Si bonding formation as reported in previous works.

Electrical characterization and carrier transportation in Hf-silicate dielectrics using ALD gate stacks for 90 nm node MOSFETs

Metal-oxide-semiconductor capacitors (MOSCs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating hafnium silicate (Hf-silicate) dielectrics were fabricated by using atomic layer deposition (ALD). The electrical properties of these Hf-silicate thin films with various postnitridation annealing (PNA) temperatures were then examined to find the best nitridation condition. It is found that the best conditions to achieve the lowest gate leakage current and best equivalent oxide thickness (EOT) are when PNA is performed at 800 °C in NH 3 ambient for 60 s. To understand the obtained film, carrier transportation mechanisms, the temperature dependence of the leakage current was measured from 300 K to 500 K for both gate injection and substrate injection. The result reveals that the leakage mechanisms involve Schottky emission at high temperature and low electrical field and Poole–Frenkle emission at low temperature and high electrical field. The barrier heights of poly-Si/Hf-silicate and Hf-silicate/Si interfaces extracted from Schottky emission are 1.1 eV and 1.04 eV, respectively. The interface traps per unit area, the mean density of interface traps per area and energy and the mean capture cross-section are determined about 8.1 × 10 10 cm −2, 2.7 × 10 11 cm −2 eV −1 and 6.4 × 10 −15 cm −2 using charge pumping method.

A Consistent Deep-Level Hole Trapping Model for Negative Bias Temperature Instability

This paper addresses a fundamental question on the physics of negative bias temperature instability (NBTI). Besides interface states, is oxide trapped charge (i.e., trapped holes) generated concurrently by NBTI stress? The discussion is made against a backdrop of critical questions, evolving from recent studies, which challenge the validity of the charge pumping method used commonly for quantifying and differentiating interface states from an oxide trapped charge. An objective and systematic analysis of dc current-voltage data reveals a broad energy distribution of stress induced positive trap states. Relative difference in the energy levels of these positive trap states determines their role as either interface states (trap states in the Si bandgap) or oxide trapped charge (deep-level trap states near and above the Si conduction band edge). This framework satisfactorily explains many electrical characteristics, known hitherto, of an NBTI-stressed p-MOSFET without specific regard to the exact origin of the traps. However, distinct relaxation characteristics of deep-level positive trap states, as compared to those of the interface states, imply a fundamental difference in the origin of these traps. Under positive gate biasing, the density of interface states is unchanged, but the density of deep-level positive trap states is significantly reduced. Electrical behavior of the deep-level positive trap states is shown to conform to that of oxide traps, implying that these trap states arise from hole trapping. However, a detailed temperature dependence study indicates that the mechanism, which is responsible for the generation of a substantial portion of the positive trap charge, has a very small activation energy (0.02 eV). This observation suggests that the generation of a significant portion of the positive trap charge is neither due to the breaking of bonds nor is rate-limited by matter transport. A possible mechanism involving a negative-field-induced loss of electronic charge from nitrogen donors is proposed.

High-Pressure Deuterium Annealing Effect on Nanoscale Strained CMOS Devices

High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices.

Gate Annealing of Cycling Endurance and Interface States for Highly Reliable Flash Memory

We report on superior cycling endurance due to a low interface trap density, which accounts for the high gate annealing temperature in flash memory. The interface trap density was characterized using a charge pumping method (CPM). The cycling VTH shift in an erase state value of 1.35 V at 850 °C temperature of an annealing, as measured on a 90-nm-technology 1-Mbit cell array, selected randomly from 1 Gbit cells, drops to less than 0.9 V after annealing at 950 °C. These superior electrical properties resulted from a complete relaxation of silicon interface trap charges due to a plasma-induced attack during gate annealing at temperatures over 950 °C for a long time. Therefore, the key factor for highly reliable endurance with cycling is believed to be the interface trap control of the thermal annealing carried out after gate etching.

Retention Reliability Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory with N2O Oxidation Tunnel Oxide

The reliability characteristics of silicon–oxide–nitride–oxide–silicon (SONOS) devices with different thin tunnel oxides are studied. The device with the tunnel oxynitride grown in pure N2O ambient at a high temperature has better performance, including better leakage current, programming speed, read-disturb, and retention characteristics, than that with a tunnel oxide layer grown by dry oxidation with N2 annealing treatment. Moreover, the properties of two-bit operation are also displayed by a reverse read method. Furthermore, the surface roughness and interface states between a tunnel oxide layer and a Si substrate are also observed by atomic force microscopy (AFM) and charge-pumping method to evaluate interfacial nitrogen incorporation. The results show that data retention reliability attained a significant improvement while maintaining good programming/erase performance and two-bit operation. This work can provide a straightforward way of reliability improvement for future flash memory application.

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ High- $\kappa$ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO2 high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10-8- 10-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling