Charge-pump Phase-locked Loop Research Articles

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and −250.8-dB FOMPLL

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs_rms Integrated Jitter and −250.8-dB FOM_PLL

Design of low power and low phase noise LC-VCO for Bluetooth/WLAN applications

The proposed Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) prototype design generates 2.45 GHz to 4.58 GHz of frequency using the Cadence UMC 180 nm process with a 1.8V supply. This architecture carried a new viewpoint on tank design put forth by enhancing the varactor tuning. Here, the circuit employs a CMOS differential cross-coupled pair, and rail-to-rail DC biasing achieves a higher voltage swing. Simulation analysis parameters are measured at 2.45 GHz frequency, phase noise is −123.5 dBc/1 MHz offset, power is 3.5 mW, jitter is 0.232 fsec, and it occupies 0.118 μm2 layout area. Additionally, the simulations have been extended for analysis under Process Voltage and Temperature Corners, Monte-Carlo, and Worst-Case Corners. This study obtained a better FoM of -200.94 dBc/Hz. The simulation results and FoM of the proposed design show a considerably improved than state-of-the-art framework. This LC-VCO circuit study will be suitable for implementing the sub-6 GHz charge pump phase-locked loops (CP-PLLs) system for 5G applications.

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated.

Wide range linearization calibration method for DFB Laser in FMCW LiDAR

In this paper, a solution based on a hybrid electro-optic phase-locked loop (HEO-PLL) is proposed to address the nonlinearity of the continuous sweep frequency of the light source in Frequency Modulated Continuous Wave (FMCW) LiDAR. This nonlinearity leads to large measurement errors, low accuracy, and poor system adaptability. The proposed solution uses a HEO-PLL to control the frequency sweep linearity of the distributed feedback (DFB) laser when it undergoes continuous, rapid, and wide-range frequency modulation through current tuning. The system is designed to allow the DFB laser to be used as a high-quality source for FMCW LiDAR. This enhances the resolution and ranging capability of the FMCW LiDAR with the DFB laser as the source, while avoiding issues such as difficult tuning of the loop bandwidth and central frequency and being highly susceptible to temperature and voltage variations caused by the charge pump phase-locked loop.

An event‐driven model of fractional‐N CPPLL based FMCW synthesizers

AbstractThis paper proposes an improved event‐driven (ED) model to improve the simulation efficiency of a mixed‐signal charge‐pump phase locked loop (CP‐PLL) design for a frequency‐modulated continuous‐wave (FMCW) chirp generation. The improvement mainly comes into three parts. First, we update the data only when it changes during the previous trigger. Second, we save the data at the triggering moment of the reference clock to achieve uniform sampling for better noise characterization. Furthermore, we propose a simplified model that is specifically optimized for the third‐order loop filter (LF). This article presents a detailed design flow of the improved ED model, and we apply it to the simulation of the FMCW chirp generation. Compared to the conventional transistor‐level simulation, our proposed model reduces the simulation time to less than 1 s, which leads to a reduction of the simulation time by five or six orders of magnitude.

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

AbstractThis paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments

This paper presents a radiation tolerant charge-pump Phase-Locked Loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage-or dose-dependent charge injection and address the limitations of Enclosed Layout Transistors (ELTs) in the conventional drain switched charge-pump. The circuit has been processed in a 65nm Complementary Metal Oxide Semiconductor (CMOS) technology and has been experimentally verified with X-rays up to a total ionizing dose of 180 Mrad.

A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology

AbstractThis paper presents a wide‐band charge‐pump phase‐locked loop (CPPLL) with reference spur reduction techniques. To broaden the frequency range without deteriorating phase noise, a 6‐bit capacitor array‐based VCO and an automatic frequency calibrator (AFC) are used. A compact loop filter technique saves the capacitor area and maintains the bandwidth. Also, a novel charge pump with dynamic current matching circuit is proposed to reduce the reference spur of the PLL. The current mismatch is less than 0.22 A (0.16%) over the voltage range from 0.75 to 1.55 V. Fabricated in 0.13 m CMOS technology, the proposed PLL achieves a locking range of 7.6–12.3 GHz (47.2%), with a 25 MHz frequency interval. The PLL consumes 23.3 mA from a 2.5 V supply voltage and occupies a core area of 0.92 mm 0.72 mm. The reference spur of the proposed PLL is measured to be −81.1 dBc, and in‐band phase noise reaches −110.8 dBc/Hz at 1 MHz offset frequency from the 9.5 GHz carrier frequency.

A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS

This article proposes a fractional-N charge pump phase-locked loop (CP-PLL) with fast two-point modulation calibration using Duty-Cycle and Polarity Tracking technique. The proposed calibration method can perform delay and gain calibration within 15 μs, respectively. A DTC-assisted Polarity Detector is used to track and countervail the propagation delay of two modulation paths. A TDC-based Duty-Cycle Detector is used to monitor and compensate the two paths gain mismatch. By comparing the code with the threshold set in the look-up table (LUT), a quick calibration can be achieved. To maintain high out-band phase noise performance and stronger robustness, a Class-C oscillator using Capacitance Desensitization technique and Cross-Bias technique is adopted in the design. The proposed CP-PLL is implemented in a standard 110-nm CMOS technology, occupying 2.7 mm2 silicon area. The post-simulation results show the proposed calibration method can calibrate the delay/gain mismatch within 30 μs. Fast calibration mode supports calibration time within 62.5 ns. The phase noise performance is −91-dBc/Hz@100 kHz, −119-dBc/Hz@1 MHz. The entire CP-PLL dissipates 20.9-mW and achieves an RMS jitter of 6.2 ps, corresponding to a figure of merit (FOM) of −211-dB.

Optimization of Performance Parameters of Phase Frequency Detector Using Taguchi DoE and Pareto ANOVA Techniques

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ([Formula: see text], [Formula: see text], and [Formula: see text]) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters [Formula: see text], [Formula: see text], and [Formula: see text] are likewise determined using this procedure to maximize the circuit’s overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are [Formula: see text] dBc/Hz, 9.83 [Formula: see text]W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 [Formula: see text]. The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 [Formula: see text]s.

Frequency Source Design of Fast Locking Laser Range Radar

Given the bad ranging precision in continuous wave laser range radar systems because of the large jitter of the main oscillator frequency source, this paper introduces the fast locking method, which is based on Field Programmable Gate Array (FPGA) and modified mixed Charge Pump Phase Locked Loop (CPPLL), effectively improving the locking time of PLL frequency source. The input frequency is generated by a temperature compensation quartz crystal oscillator with high stability frequency (TCXO). It improves the PLL performance using the two-order active filter, reduces the phase detector dead-banding, and improves the frequency stability through the buffer insertion in PFD. The traditional PLL was improved by using preset voltage mode, which improves the PLL lock time. Finally, it analyzes the influence of frequency stability on the ranging accuracy of laser radar. The test results show that PLL lock time is up to 1.6ms. It can be applied to continuous wave laser radar ranging systems.

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal-oxide-semiconductor process.

A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits

In this article, a cryo-CMOS receiver integrated with a frequency synthesizer for scalable multiplexed readout of qubits is presented, focusing on radio frequency (RF) reflectometry readout of silicon-based semiconductor spin qubits/quantum dots. The proposed spin qubit readout chip consists of a wideband low noise amplifier (LNA), a quadrature mixer, a complex filter, a pair of in-phase/quadrature (I/Q) intermediate frequency (IF) amplifier chains, and a type-II charge-pump phase-locked loop (PLL) with a programmable frequency divider providing local oscillator (LO) signals. Noise optimizations are applied to the LNA design and the quadrature active mixer design to obtain the required performance. A mode-switching complementary voltage-controlled oscillator (VCO) is proposed to achieve low-power and low-phase noise in a wide-frequency tuning range (46.5%). Circuit modifications and design considerations for robust cryogenic temperature operation are presented and discussed. Measurements show that the receiver provides an average gain of 65 dB, a minimum noise figure of 0.5 dB, an IF bandwidth of 0.1–1.5 GHz, and an image rejection ratio of 23 dB at 3.5 K with a power consumption of 108 mW. This cryo-CMOS receiver with frequency synthesizer for spin qubit readout is a first step toward fully-integrated qubit readout and control.

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

AbstractA low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption.

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm2, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.

A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity

This article presents a low supply voltage and low-power charge-pump phase-locked loop (CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {ref}}$ </tex-math></inline-formula> adaptive adjustment mechanism is analyzed in the class-C voltage-controlled oscillator (VCO) with dual-mixed loops, which eliminates the PN’s sensitivity to temperature and process. Moreover, based on resistance-based accurate current replication, the low-power and low-current mismatch charge-pump (CP) circuit structure is proposed to reduce the reference spur of the PLL. In addition, by using the dynamic current compensation scheme, the power consumption of the CP is greatly reduced. The proposed PLL is fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> RF CMOS process with an area of 1.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the proposed PLL achieves a 2.24–2.85-GHz frequency tuning range and a PN of −123.97 dBc/Hz at 1-MHz offset from a 2.55-GHz carrier. The measured reference spur is −89.4 dBc at 40-MHz offset frequency and the total power consumption is 2.62 mW at the 0.8-V power supply voltage.