Charge-pump Phase-locked Loop Research Articles

A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator

A 6-GHz phase-locked loop based spread-spectrum clock generator employing a self-oscillating technique is proposed. The clock generator adopts the property of the inherent oscillation of a charge-pump PLL while introducing no extra quantization noise. With the amplitude and frequency control, modulation frequency and frequency deviation can be tuned at 31.5 kHz and 5000 ppm, respectively. The measured EMI reduction is 12.5 dB at the 100-kHz resolution bandwidth. The measured root mean square jitter is 2 ps and peak-to-peak is 15 ps. This work was fabricated in a 90-nm digital CMOS technology, occupies 0.54 and consumes 14.4 mW from a 1.2-V supply.

Phase Noise Modeling for Integrated PLLs in FMCW Radar

The effect of frequency modulation (FM) on the phase noise spectrum of a charge pump phase-locked loop (PLL) for frequency-modulated continuous-wave (FMCW) radar is investigated. The static phase error is calculated as a function of frequency ramp slope and basic PLL design parameters. The phase noise spectrum under FM is deduced from the spectrum in the steady state. Design guidelines for integrated PLLs to be used in FMCW radar are derived from theoretical considerations and experimental results from the literature.

A new fast locking charge pump PLL: analysis and design

In this paper a new structure for a fast locking charge pump phase locked loop (CPPLL) is introduced which overcomes the trade-off between the settling time and overshoot of the system. This fast locking PLL uses an auxiliary bang---bang frequency comparator (BBFC) as a lock-aid. An additional charge pump current controlled by the output of the BBFC is injected into the main loop filter capacitor to accelerate the locking process. An analytical approach to extract the differential equation governing on the system's dynamics is used to evaluate the performance of this fast locking PLL. A heuristic method that results in an approximate solution for the extracted differential equation is also proposed. The correctness of the presented differential equation and its closed-form solutions are verified by comparing the obtained closed-form solutions and simulation results. Using the obtained closed-form solutions, we predict the behavior of the system and design a fast BBFC-CPPLL which meets the system's requirements. Correctness of the differential equation and its closed-form solutions are verified by comparing the obtained closed-form solutions and simulation results.

Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops

In this work, a monotonic increasing piecewise-linear (PWL) memristor-based proportional-integral (PI) controller is analyzed. A periodic rectangular pulse current source is used as the input signal, and the proportionality constant of the PWL memristor-based PI controller is varied according to the amount of charge that passes through the memristor. A circuit is proposed to achieve zero net-charge injection for the memristor so that the memristance of the PWL memristor can be varied in the subsequent period. The proposed PWL memristor-based PI controller can be used in the design of the loop filter for the charge-pump phase-locked loop for achieving a faster dynamical response from an unlocked state to a locked state compared to conventional fixed proportional constant PI controllers.

Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops

This paper presents a phase noise analysis of charge-pump phase-locked-loops. Fundamental results from the theory of discrete-time systems are employed to derive closed-form expressions of noise transfer functions and design guidelines. The proposed expressions allows predicting the PLL in-band noise and spurs induced by VCO internal white and flicker noise sources and by external interferences coupled to VCO most sensitive nodes. To verify the correctness of the presented theoretical results, a simulation method is developed, which takes into account the time-varying nonlinear characteristics of the VCO and which is much more efficient than transistor-level noise simulations.

A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-μm 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are 400 × 450 μm2 and 6 mW, respectively.

Dynamics of charge-pump phase-locked loops

Certain problems in the existing treatment of the stability of charge-pump phase-locked loops are identified and addressed in this work. New results concerning the instability, stability, and asymptotic stability of charge-pump phase-locked loops are obtained by means of Lyapunov's direct and indirect methods. Closer consideration of the local dynamics provides further insight into the system's patterns of behavior. In particular, the influence of circuit parameters on the nature of the steady-state orbits is investigated. Copyright © 2012 John Wiley & Sons, Ltd.

An LMI-Based Method for Reference Spur Reduction in Charge-Pump Phase-Locked Loops Containing Loop Delay

This paper presents a loop-filter design method for third-order charge-pump phase-locked loops containing the loop delay. This method is derived from a z-domain phase-locked loop model. For a given loop bandwidth, we employ ripple swing control and adjust the filter pole to improve the spur performance. Another dynamic specification, the jitter peaking, is formulated as a H ∞ performance. The loop-filter design is transformed into an H ∞ optimization problem with the ripple swing constraint, which is solved using convex programming skills (linear matrix inequality, LMI). Compared to the conventional method, the method proposed in this study offers greater spur reduction without altering the loop bandwidth.

Nonlinear behavioural model of charge pump PLLs

SUMMARY Despite the nonlinear nature of even the simplest versions of phase locked loops (PLLs), linear models are still used during the first phases of the design of modern PLLs. Even though the linear model may represent a crude approach, its use is justified by the fact that accurate numerical simulations often require a too large amount of CPU time, being PLLs by construction stiff circuits, characterised by very different time scales. This aspect has triggered the need for compact models that allow fast and accurate numerical simulations. The scientific literature numbers several models that have been developed with different approaches and tailored to different simulation environments. In this context, we propose a nonlinear model of a type-II PLL, which (1) considers both the switching behaviour of the phase/frequency detector and charge pump and the complex dynamics (including the presence of amplitude and phase noise) of the voltage controlled oscillator, (2) is compact and can be easily implemented in modern mixed analog/digital simulators as a behavioural block, and (3) allows the simulation of spurs owing to the nonlinearities of both the charge pump and the fractional frequency divider. Copyright © 2012 John Wiley & Sons, Ltd.

A systematic procedure for analysis of third-order charge pump phase-locked loop (PLL)

This paper represents a simple and easy to learn method for analysis and design of third-order charge pump phase-locked loop (PLL) and provides analytical equations for calculating the desired specifications such as phase margin (PM), damping ratio and small signal settling time. The proposed method is based on dominant pole approximation. In other words, this method is based on the approximation of the transfer function of the third-order PLL through transfer function as a second order system. The validity of the obtained analytical equations has been verified in two examples. Simulation results of the introduced method demonstrate precision in designed parameters. Key words: Charge pumps phase-locked loop (PLL), phase detector, phase margin (PM), settling time, damping ratio, natural frequency.

System- and circuit-level optimization of PLL designs for DVB-T/H receivers

This article proposes a framework for the optimization of voltage-controlled oscillator (VCO) designs in frequency synthesizers for digital video broadcasting --- terrestrial/handheld (DVB-T/H) receivers. Linear time-invariant phase-domain model of a charge-pump phase-locked loop (PLL) is devised and includes both flicker (1/f) and thermal noise contributions from the loop oscillators. By modeling the entire receiver, it is shown that there are combinations of flicker and thermal noise contributions that result in a constant sum of inter-carrier interference (ICI) and adjacent channel interference, and constant symbol error rate as well. Consequently, optimization of the VCO phase noise spectrum is defined while maintaining the standard-specified symbol-error rate. Link-level performance evaluation is carried out to validate the stipulated trade-off. The effect of ICI mitigation schemes is discussed. Circuit-level VCO design approaches utilizing the derived trade-off are finally presented. The proposed optimization procedure is generic and is also applicable to other systems based on Orthogonal Frequency-Division Multiplexing.

PLL charge pump with adaptive body-bias compensation for minimum current variation

A novel charge pump with adaptive body-bias compensation to minimise the current variation over a wide output voltage range is proposed. With 1.2 V supply voltage, the proposed charge pump demonstrates a constant current of 140 μA across the output voltage from 0.2 to 1.0 V. The current variation is less than 1.20 μA or 0.9 over output range, which helps keep the loop bandwidth of the charge pump phase-locked loop (PLL) fixed and maximise the dynamic range. Extremely low power adaptive bias circuits are proposed to provide body-bias compensation at different output voltage levels. It is believed that the current variation is the minimum among the published results of PLL charge pumps.

On the simulation of fast settling charge pump PLLs up to fourth order

AbstractIn this paper, we discuss three different models for the simulation of integer‐N charge‐pump phase‐locked loops (PLLs), namely the continuous‐time s‐domain and discrete time z‐domain approximations and the exact semi‐analytical time‐domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time‐domain model are introduced and the results are compared with those obtained by means of the s‐domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB‐OFDM UWB systems. Copyright © 2010 John Wiley & Sons, Ltd.

Computing low-frequency noise in charge-pump phase-locked loops

An efficient simulation method to compute the low-frequency noise spectrum found at the output of charge-pump phase-locked loops is described. It is investigated how such a noise component varies as a function of the division factor.

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed. In the CCL-LDO, the control method of the charge pump phase-locked loop is adopted. A current control loop has the feedback signal and reference current to be compared, and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current. The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-1-V and is not restricted by the reference voltage. With a 1 μF decoupling capacitor, the experimental results based on a 0.13 μm CMOS process show that the output voltage is 1.0 V; when the workload changes from 100 μA to 100 mA transiently, the stable dropout is 4.25 mV, the settling time is 8.2 μs and the undershoot is 5.11 mV; when the workload changes from 100 mA to 100 μA transiently, the stable dropout is 4.25 mV, the settling time is 23.3 μs and the overshoot is 6.21 mV. The PSRR value is more than −95 dB. Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers.

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver

A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication and voltage integration. Power consumption of the charge-domain receiver is minimized by a novel auto- and cross-correlation based synchronization scheme. To reduce the power consumption and the chip area of the PLL clock generator for the receiver, a dual charge-pump PLL is proposed to scale up the capacitance of the loop filter without extra charge-pump current. The developed UWB receiver with the area- and power-efficient PLL achieves the energy consumption of 29.3 pJ/bit with the 62.5-ps timing step for data synchronization.

카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 ㎓ charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5㎂ current mismatch in CP. It was designed in a standard 0.13㎛ CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38㎽ with 1.5V power supply and effective area is 0.1804㎟.

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage.