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Abstract
A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 ㎓ charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5㎂ current mismatch in CP. It was designed in a standard 0.13㎛ CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38㎽ with 1.5V power supply and effective area is 0.1804㎟.
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