Charge Pump Circuit Research Articles

Gate-Oxide Voltage Overstress Treatment in Charge Pump Circuits for Standard CMOS Technologies

Charge pump circuits operating at voltage levels above that of the power supply usually suffer from gate-oxide voltage overstress. Such reliability problem has become a concern especially as the gate-oxide thickness is scaled down. Devising charge pump circuits that avoid such a problem is far simpler for CMOS triple-well technologies than for standard technologies, nevertheless fabrication costs are higher. Two approaches are usually applied to eliminate gate-oxide overstress in charge pumps designed for standard CMOS technologies, the first is multiple phase control, and the second is dual phase control with doubled voltage swing. The latter has been shown to produce more power efficient circuits, however solutions using such approach still present gate-oxide overstress in some transistors. In this work, it is shown that a slight change in some of the circuit connections is able to ultimately overcome the problem. Moreover, experimental results have shown that such circuit topology can reach a voltage multiplication efficiency of about 98 %.

Fully implantable, multi‐channel microstimulator with tracking supply ribbon, multi‐output charge pump and energy recovery

A novel energy-efficient approach dedicated to high-density implantable stimulators such as visual prostheses is presented. Energy efficiency of the approach proposed in this work is achieved through two ideas: the ‘tracking supply ribbon’ technique and ‘reverse charge pumping’. The proposed approach is implemented, in the multi-channel case, in such a way that power efficiency of each stimulation channel is enhanced according to its specific voltage/current condition and independently from other channels. For this purpose, a multi-channel power-efficient charge pump circuit with small integrated capacitors is proposed. Based on the proposed approach, a fully integrated 16-channel stimulation backend for a visual prosthesis was designed and simulated in the transistor level in a standard 0.18-μm triple-well CMOS technology, occupying 1.41 mm2 of silicon area. According to post-layout simulation results, power savings of up to 74% for a single channel and 81.5% for multiple channels are achieved compared to the conventional output stage with a constant supply voltage. Designed for the proposed stimulation backend, the charge pump generates output voltages of 3.48 V, −1.69 V, −3.38 V, and −5.05 V out of a 1.8 V input voltage and exhibits average power efficiency of 92.8% and 86.8% for one- and three-stage circuits, respectively, all in the case of a 100 μA current load. All the aforementioned results are based on post-layout simulation. Moreover, a proof-of-concept prototype was developed using off-the-shelf components in order to demonstrate the operation of the proposed tracking supply ribbon idea.

An Optimum Design of Clocked AC-DC Charge Pump Circuits for Vibration Energy Harvesting

This paper shows how clocked AC-DC charge pump circuits can be optimally designed to have the minimum circuit area for small form factor vibration energy harvesting. One can determine an optimum number of stages with simple equations and then determine the capacitance of each pump capacitor to have a target output current at a target output voltage. The equations were verified under a wide range of design parameters by comparing the output current with the simulated one. The output current of the circuit designed by the equations was in good agreement with the simulated result, to within 5% for 98% of the 1600 designs with different parameters. We also propose a design flow to help designers determine the initial design parameters of a clocked AC-DC charge pump circuit (i.e., the number of stages, capacitance per stage, and the total size of rectifying devices) under the condition that the saturation current of a unit of the rectifying device, clock frequency, amplitude of the voltage generated by the energy transducer, target output voltage, and target output current are given. SPICE simulation results validated theoretical results with an error of 3% in terms of the output current when a clocked AC-DC charge pump was designed to output current of 1 μA at 2.5 V from a vibration energy harvester with an AC voltage amplitude of 0.5 V.

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Charge-pumping with finger capacitance in a custom electrostatic energy harvesting ASIC

We present an integrated circuit capable of scavenging energy from repetitive changes in finger touch capacitance. A finger tapping on this application-specific integrated circuit generates a capacitive change of approximately 770 pF. This change feeds into a charge-pump circuit that stores 320 pJ of energy on a 1 nF storage capacitor. We present measurement results and simulations that demonstrate operation. As a proof-of-concept, we also demonstrate that the harvested energy can power a ring oscillator that outputs a series of chirps with frequencies ranging from 80 Hz to 30 kHz as the storage capacitor voltage charges and discharges.

An extended high-voltage-gain DC–DC converter with reduced voltage stress on switches/diodes

A new transformer-less boost-based DC–DC converter is suggested in this research. The voltage gain of the proposed converter is enhanced employing a charge-pump circuit (CPC) and n-stages of voltage multiplier cells (VMC). Each VMC consists of one inductor, one diode, and two capacitors. As the number of these VMC stages (n) increases, it is feasible to achieve high voltage gains with low duty cycles. Furthermore, by expanding n, a significant reduction of the normalized peak voltage stress (NPVS) of the components is possible. Due to this feature, using the MOSFET switches with low ON-state resistance and the low-rating voltage components is provided which results in diminishing the conduction and switching losses. The steady-state analysis is accomplished in details and the comparison considering other converters in the literature is presented in this manuscript. Validating of the converter performance is accomplished by implementing a laboratory prototype for the power of 300 W, input, and output voltages of 30 V and 310 V, respectively, and switching frequency of 40 kHz. Experimental results validate the mathematical analysis.

A Glucose Monitoring System With Remote Data Access.

A cost-effective portable glucose monitoring system with remote data access based on a novel e-oscilloscope was developed using a glucose biofuel cell and a capacitor circuit interfaced to an ESP8266 microcontroller programmed to convert the charge/discharge rates of the capacitor functioning as a transducer. The capacitor charge/discharge rates were converted into glucose concentration readings that is monitored remotely. The glucose monitoring system comprise a glucose biofuel cell, a charge pump circuit, a capacitor and an ESP microcontroller. The anode was fabricated by modifying a gold microwire with nanoporous colloidal platinum (Au-co-Pt) and the cathode was constructed using a mesh dense network of multiwalled carbon nanotubes modified with bilirubin oxidase, respectively. The glucose monitoring system showed sensitivity of 1.18 Hz/mM · cm2 with a correlation coefficient of 0.9939 with increasing glucose concentration from 1 mM to 25 mM. In addition, the glucose monitoring system exhibited optimal operation at a pH of 7.4 and 37 °C, which is ideal for physiological glucose monitoring.

Low‐voltage charge pump circuit with double boost technique

AbstractIn recent years, interest in IoT (Internet of Things) has been increasing, and energy harvesting has attracted attention. However, the power and voltage that can be harvested are very small. Therefore, a power supply circuit is required to solve this problem. In this paper, we have realized a boost circuit that does not require a coil with the aim of integrating all the circuits required for sensing on one chip.

Asymmetric diode-clamped multi-level inverter based renewable power generation system

ABSTRACT In this paper, a grid-connected power conversion topology is developed to convert a DC power from the renewable energy into a high-quality AC power. This grid-connected power conversion topology consists of an asymmetric diode-clamped multi-level inverter (DCT-MLI) and a dual-output DC-DC power converter. The asymmetric DCT-MLI includes two diode-clamped arms, two DC capacitors, and a filter inductor. The novelty of proposed asymmetric DCT-MLI is that the voltages of the two DC capacitors are in a multiple relationship. As a result, the asymmetric DCT-MLI will generate an AC voltage with more voltage levels by the power circuit similar to the symmetric DCT-MLI, and the capacity of filter inductor is further reduced. The dual-output DC-DC power converter combines a boost converter and a charge pump circuit to generate two DC voltages in a multiple relationship to supply the asymmetric DCT-MLI. The salient feature is that only a power electronic switch is used in the dual-output DC-DC power converter such that the control circuit is simplified. A hardware prototype is set up to verify the performances of the proposed grid-connected power conversion topology.

Charge Pump Gate Drive to Reduce Turn-ON Switching Loss of SiC MOSFETs

Turn- on loss is the dominant part of the switching loss for SiC MOSFET s in hard switching. Reducing turn- on loss with conventional voltage source gate drives (VSGs) is difficult because of the limited gate voltage rating and large internal gate resistance of SiC MOSFET s. A charge pump gate drive (CPG) that can reduce the turn- on loss is presented in this article. By precharging the charge-storage capacitor in the gate drive with a charge pump circuit, the gate drive output voltage is pumped up to provide higher gate current during the turn- on transient. As a result, the turn- on time and loss is decreased. Moreover, due to the charge transfer from the charge-storage capacitor to the MOSFET gate capacitance, the pumped output voltage can naturally drop back to a normal value that avoids gate overcharging. The structure of the gate drive is simple, and no additional control is needed. The operation of the proposed CPG is verified with double pulse tests based on SiC MOSFET s. The switching loss of the proposed CPG is reduced by up to 71.7% compared to the conventional VSG at full load condition.

Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging

This brief proposes a simple but effective strategy to improve wake-up operation in energy-autonomous systems which exploits Charge Pump (CP) circuits to boost voltage directly from energy harvester generators. By means of few auxiliary diodes and parasitic junctions, the CP is managed to retain the charges in the pumping capacitors when the harvesting power source is not able to feed the system, thereby reducing the rise time and input energy demand during the start-up phase. Simulation results using a 65-nm CMOS technology confirm the potentialities of the proposed strategy and show a reduction of the rise time and the input energy higher than 20% as compared with the traditional topology.

A Low Input Voltage Charge Pump for Energy Harvesting

This paper proposes a low input voltage charge pump using 0.18um CMOS process for energy harvesting. There are two main sections in the charge pump system: Low Voltage Charge Pump (LVCP) and High Voltage Charge Pump (HVCP). In the LVCP, a negative charge pump is utilized to improve the efficiency at low input voltage, Dynamic Body Bias (DBB) and switch-conductance enhancement techniques are applied to a unit stage of the two-stage charge pump. In the HVCP, the charge pump circuit utilizes charger transfer switches (CTS) with a complementary banch scheme to significantly reduce undesired charge transfer, and an optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. The simulation result demonstrates that the proposed circuit can achieve 97% voltage conversion and drive 800uA load current at 0.6V input voltage. In the region of 0.4V to 0.6V input voltage, the circuit performs well with the load resistance of 10K ohms.

A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit

In this brief, a low quiescent output-capacitor-less NMOS low-dropout regulator using a coarse-fine charge-pump circuit is proposed. The proposed charge-pump low-dropout regulator (CP-LDO) achieves the output-capacitor-less LDO using a NMOS power transistor, a comparator, and a coarse-fine charge-pump circuit. It reduces both the quiescent current and the capacitor size of the charge-pump by directly adjusting the gate voltage of the NMOS power transistor. It improves both the transient response and the quiescent power efficiency by coarsely and finely adjusting the gate voltage, respectively. This also can remove the output glitch voltage. The proposed CP-LDO was fabricated using a 65nm CMOS process. Its area is 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The maximum undershoot voltage is 108 mV when the load current changes from 0.5 mA to 10.5mA within the edge time of 1ns. The total capacitor of the CP-LDO is 7.6 pF. The quiescent current is 162 nA at VIN = 0.5 V and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> = 1 MHz. The figure of merit is 0.0013 ps.

Analysis and Design of a Charge-Pump-Based Resonant AC–DC Converter With Inherent PFC Capability

This article presents the analysis and design of a resonant power factor correction (PFC) rectifier for the first stage in single-phase front-end offline converters targeting low-power applications (up to 100 W). With the addition of a charge-pump circuit comprised of a capacitor and a diode to a class-DE resonant converter, PFC functionality is achieved inherently. The operation is based on soft switching, allowing for increased switching frequencies with reduced switching losses. A 1-MHz prototype employing wide bandgap switching devices is built and tested to validate the analysis and proposed design method. The prototype achieves up to 50 W of output power with a power factor of 0.99, a total harmonic distortion of 8.6%, and an efficiency of up to 88%; with harmonic magnitudes well-within the IEC 61000-3-2 standard class-C device limits, making it suitable for use as the rectifier stage in light-emitting diode (LED) drivers. Despite the additional circuit stresses from the charge-pump operation, the proposed converter offers simplicity and low component overhead, with the potential for higher frequency operation toward higher power densities.

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM.

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis

Performance failure has become a major threat for various memory and analog circuits. It is challenging to estimate the extremely small failure probability when failed samples are distributed in multiple disjoint regions. In this article, we propose an adaptive importance sampling (AIS) algorithm. AIS has several iterations of sampling region adjustments, while existing methods predecide a static sampling distribution. We design two adaptive frameworks based on resampling and population Metropolis–Hastings (MH) to iteratively search for failure regions. The experimental results of the AIS method exhibit better efficiency and higher accuracy. For SRAM bit cell with single failure region, the AIS method uses 2– $27{\times }$ fewer samples and reaches better accuracy when compared to several recent methods. For a two-stage amplifier circuit with multiple failure regions, the AIS method is $90{\times }$ faster than Monte Carlo and 7–23 ${\times }$ over other methods. For charge pump circuit and $C^{2}MOS$ master–slave latch circuit, the AIS method can reach 6– $18{\times }$ and 4– $6{\times }$ speedup over other methods, respectively.

Low Voltage Charge Pump Circuit with Double Boost Technique

Low Voltage Charge Pump Circuit with Double Boost Technique

Low-Voltage Capacitive-Based Step-Up DC-DC Converters for RF Energy Harvesting System: A Review

Bulky off-chip inductors are predominantly adopted for inductive-based step-up DC-DC converter in RF energy harvesting (RFEH) systems, which impose a restriction in physical form factor for miniaturized device. This article review and explores the capacitive-based step-up DC-DC converters (charge-pump) as voltage boosting element for low-voltage RFEH systems. An overview of RFEH is established and a comprehensive review of CMOS charge-pump is followed along with the complementary frequency generation circuit used as a clocking element. Key design considerations of charge-pump circuits are included here along with recommendations to circumvent its bottlenecks for future development in RFEH systems.

Nano CMOS Charge Pump for Readerless RFID PLL

Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLLs) are among the most crucial functional blocks in the Readerless RFID where the PLL performance greatly depend on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. In order to overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintain the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V and the core occupies 17 x 59.5 μm 2 . The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performances.

A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency

A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency fabricated by IHP’s 130 nm SiGe BiCMOS process is proposed. Instead of traditional on-chip metal–insulator–metal capacitor, a modified vertical parallel plate capacitor is utilized as the pumping capacitor, which owns a breakdown voltage higher than 84 V and an improved capacitance density of 1.92 fF/μm2. Thus, the output voltage and chip size of charge pump circuit are not limited by the pumping capacitor. To further improve the voltage pumping efficiency and make the circuit suitable for low voltage operation, the threshold voltage and the body effect coefficient is eliminated by using a dynamic control to both the charge transfer switches and the MOSFETs body voltages. Simulated result of a 35-stage charge pump circuit with an output voltage higher than 100 V is demonstrated. A 7-stage charge pump circuit with an output voltage of 13.8 V and a pumping efficiency of 75%, higher than the traditional Dickson’s charge pump circuits, is fabricated and measured.