Abstract
Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLLs) are among the most crucial functional blocks in the Readerless RFID where the PLL performance greatly depend on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. In order to overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintain the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V and the core occupies 17 x 59.5 μm 2 . The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performances.
Highlights
At present, Readerless RFID systems are experiencing rapid growth because of the advancement of the wireless communication system
Compared to results mentioned in table 1, it can be concluded that the proposed charge pump circuit has the lowest power consumption of 0.178 mW and provides the lowest current mismatch by using the current mirror and chain inverter technique which leads to a high-performance Charge pump based PLL (CPPLL)
The CP output parameters have a large impact on Phase Locked Loop (PLL) performance
Summary
Readerless RFID systems are experiencing rapid growth because of the advancement of the wireless communication system. By decreasing the current variation and mismatch, the performance of CP can be significantly improved This reduces the PLL’s spurs and static phase offset. The current mismatch in [7] is reduced by executing a differential CP with an active loop filter (LF) and common-mode feedback scheme This scheme integrated an op-amp, an analog adder, and a reference voltage circuit. The approach with double stage op-amps in three rail-to-rail amplifiers is competent and established for reducing the current mismatch It adjusts the current mirror gate bias that results in matching the output of the switch current with the drain current. It reduces the static phase offset significantly and minimizes the current mismatch. This article proposes an improved CP design in 130 nm CMOS process based on the current mirror method employing an inverter at the gates of transistors for providing a rail-to-rail voltage swing to accomplish adequate current matching
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