Charge Pump Circuit Research Articles

Study on 5.8-GHz Single-Stage Charge Pump Rectifier for Internal Wireless System of Satellite

To reduce the weight of a satellite, an internal wireless system (IWS) for satellites was proposed in a previous study. It is a system that can communicate between the satellite's subsystems by using wireless communication modules. In this paper, we propose a complete IWS for a satellite using microwave wireless power transmission technology. The design of a 5.8-GHz high efficiency rectifier circuit-based charge pump circuit is also presented. Furthermore, we introduced a class-F load that can process the third harmonic components. The rectifying efficiencies of a normal charge pump rectifier and a charge pump rectifier with the class-F load are theoretically compared. To improve the conversion efficiency of the charge pump rectifier, the applied voltages of diodes are adjusted. Owing to inserting the class-F load and adjusted the applied voltage of diodes in this circuit, the conversion efficiency of the charge pump circuit at 30 mW increases to about 78% at 30 mW in the simulation, and to about 71% conversion efficiency in the experiment. In addition, the output voltage is higher than 5 V at an optimal load 1300 Ω.

A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

A 2-2 cascaded switched-capacitor ΣA modulator is presented for design of low-voltage, low-power, broadband analog-to-digital conversion. To reduce power dissipation in both analog and digital circuits and ensure low-voltage operation, a half-sample delayed-input feedforward architecture is employed in combination with 4-bit quantization, which results in reduced integrator output swings and relaxed timing constraint in the feedback path. The integrator power is further reduced by sharing an op amp in the two integrators in each stage and periodically changing the op amp bias condition between a high-current and a low-current mode using a fast low-power high-precision charge pump circuit. Implemented in a 0.18-μm CMOS technology, the experimental prototype achieves a 92-dB dynamic range, a 91-dB peak signal-to-noise ratio, and an 84-dB peak signal-to-noise plus distortion ratio, respectively for a signal bandwidth of 1.25 MHz. Operated at a 40-MHz sampling rate, the modulator dissipates 24.3 mW from a 1 V supply.

A New Photovoltaic System Architecture of Module-Integrated Converter with a Single-sourced Asymmetric Multilevel Inverter Using a Cost-effective Single-ended Pre-regulator

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 \(\upmu \)A current. This charge pump is designed and simulated in TSMC 0.18 \(\upmu \)m CMOS technology in order to be used in a delay-locked loop. One of the benefits of this circuit is its capability to be applied in a wide frequency range from 50 to 800 MHz with power consumption range of 410–740 \(\upmu \)W. The proposed charge pump exploits feedback loop in order to achieve suitable current matching and also has a good characteristics in high frequencies.

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 μA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

Electrostatic Energy Harvesting Circuit with DC-DC Convertor for Vibration Power Generation System

This paper presents an interface circuit with power control features for electrostatic vibration energy harvesting. A DC-DC convertor is used to control the output voltage of a diode-based charge pump circuit. Therefore, the maximum and minimum voltage across the variable capacitor of the energy harvester may be adjusted to track the maximum power point of the system. The power conversion function of the DC-DC convertor depends on the switches configuration. An example of Maximum Power Point Tracking (MPPT) for different conversion function is presented in this paper. Simulation results show that at least 10 μW is generated.

Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes

Abstract Charge pumps are circuits that produce the voltage higher than supply voltage or negative voltage. Today, charge pumps became an integral part of the electronic equipment. The integration of charge pumps directly into the system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is reduced by many phenomena. This paper is focused on the question of efficiency of proposed variant of the charge pump. In this article, the efficiency dependence on a number of stages, output current, clock frequency and MOSFETs sizes was simulated by Eldo. The aim of this study is to determine the MOSFETs sizes and theirs influence to efficiency and the output voltage. Complex optimization of the charge pump circuit will follow in further text.

Continuous operation of an ultra-low-power microcontroller using glucose as the sole energy source

An ultimate goal for those engaged in research to develop implantable medical devices is to develop mechatronic implantable artificial organs such as artificial pancreas. Such devices would comprise at least a sensor module, an actuator module, and a controller module. For the development of optimal mechatronic implantable artificial organs, these modules should be self-powered and autonomously operated. In this study, we aimed to develop a microcontroller using the BioCapacitor principle. A direct electron transfer type glucose dehydrogenase was immobilized onto mesoporous carbon, and then deposited on the surface of a miniaturized Au electrode (7mm2) to prepare a miniaturized enzyme anode. The enzyme fuel cell was connected with a 100 μF capacitor and a power boost converter as a charge pump. The voltage of the enzyme fuel cell was increased in a stepwise manner by the charge pump from 330mV to 3.1V, and the generated electricity was charged into a 100μF capacitor. The charge pump circuit was connected to an ultra-low-power microcontroller. Thus prepared BioCapacitor based circuit was able to operate an ultra-low-power microcontroller continuously, by running a program for 17h that turned on an LED every 60s. Our success in operating a microcontroller using glucose as the sole energy source indicated the probability of realizing implantable self-powered autonomously operated artificial organs, such as artificial pancreas.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz.

Power efficient SRAM design with integrated bit line charge pump

Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction.

Study of Recent Charge Pump Circuits in Phase Locked Loop

This paper reviews the design of phase locked loop (PLL) using recently reported charge pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump circuit are investigated. Though improved charge pump circuits are designed recently, their performance is not as effective as the basic charge pump PLL (CP-PLL). Initially the design of PLL using the basic charge pump is completed in this paper and then the PLL using improved charge pumps are redesigned in CMOS 180 nm technology and simulated using Cadence Virtuoso Analog Design Environment. Finally all the charge pumps are compared with respect to the PLL performances. The current starved voltage controlled oscillator (VCO) used for the design of PLL brings about a tuning range of 119.5 MHz to 2.3 GHz. The PLL using different charge pumps produces a lock time which varies from 204 ns to 329 ns. The other parameters like lock range, phase noise and reference spur are also examined.

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

A Novel High Gain SEPIC Converter with the Tapped Inductor Model Operating in Discontinuous Conduction Mode for Power Factor Correction

Power Factor Correction (PFC) has become one of the most active research areas in the field of power electronics due to the surplus power required for various industrial applications around the world. In this work, a novel SEPIC converter with the Tapped Inductor model operating in Discontinuous Conduction Mode (TI-SEPIC- DCM) is proposed for PFC. The proposed TI-SEPIC-DCM improves the voltage gain through voltage multiplier cell and charge pump circuit. The voltage multiplier cell also helps in attaining the Zero-Voltage Switching (ZVS) and Zero-Current Switching (ZCS), which results in higher switching frequency and size reduction. Moreover, a third order harmonic reduction control loop has been proposed for better harmonic mitigation. The proposed work has been simulated in MATLAB and the results are obtained to validate the significance of the proposed TI-SEPIC- DCM with near unity power factor and reduced harmonics.

Стенд для исследования характеристик микросхем источников вторичного электропитания с накачкой заряда

An automated test bench for the study of the characteristics of various kinds of chips of mobile sources of regulated charge pump secondary power supply receiving energy from batteries was created. Having a modular structure, the test bench includes, in addition to the test charge pump module, power supply, control, load, display modules, and a USB module for connection with a computer. The test bench enables carrying out research of various types of chips by changing only one small measuring board. The control module is based on PIC18F2550 microcontroller. The automated measuring system consists of a multimeter and oscilloscope. The investigated characteristics are output voltage as a function of load current, output voltage as a function of supply voltage, the forms of the output voltage ripple, the response of chips to a stepped load transition. One of the major goals of the research is to study algorithms of the charge pump circuits. A program for controlling the test bench by creating a virtual front panel was developed. Together with a virtual panel of the oscilloscope and available multimeter software this allows controlling the equipment operating parameters and making measurements remotely over the Internet. Using the created test bench new experimental data on all of the above characteristics for MAX1759 chip were obtained, and an algorithm of this chip in the buck mode operation was studied for the first time.

Integrated charge pumps: a generalised method for power efficiency optimisation

Charge pumps (CPs) represent the most common solution for the implementation of fully integrated DC–DC converters. In fact, as opposed to buck/boost DC–DC converters, that need at least an external inductor, charge pump circuits do not require any external component. However, the achievable power efficiency of these circuits is typically significantly lower than power efficiency of buck/boost DC–DC converters. In this study, we develop a general mathematical model of CPs, aiming to provide basic design considerations for power efficiency optimisation. A quality factor for achievable power efficiency is proposed together with guidelines for the design of efficiency-optimised CPs under the constraint of given output voltage and current values.

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

A charge pump with a 0.32 % of current mismatch for a high speed PLL

A charge pump is a widely used circuit in modern PLLs. In order to reduce phase offset, and decrease spurs tones in the PLL output signals, the charge pump current mismatch has to be minimized. In this paper, a charge pump circuit with low current mismatch characteristic that was designed with a standard 0.18 $$\upmu $$μm CMOS technology. A Mentor Graphics environment using Eldo program was used to carry out the schematic, layout, and post-layout simulations. Under 1.8 V DC supply voltage, and 100 $$\upmu $$μA output current, the circuit consumes only 0.56 mW in fully differential mode, and 0.38 mW for a single ended configuration. Using the same bias current for UP, and DN signals, and three wide-swing current mirrors a 0.32 % current mismatch with a 0.3---1.5 V wide output voltage range was achieved. The circuit can be widely used in either single-ended or fully differential phase locked loop structures.

Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization

This brief presents a tool for optimizing the energy and delay (E/D) of static RAM designs to meet a specific die yield constraint. This allows the tool to account for the effects of process variation and to trade off yield with performance and energy. To accomplish this, we use a combination of simulation and modeling techniques to determine the minimum wordline (WL) pulsewidth required for both the read and write operations to meet a user-specified die yield. The use of a hierarchical model enables us to calculate the E/D of a full macro that is margined to meet a specific die yield. By sweeping across the possible design space, we are able to identify Pareto optimal designs. The tool structure described in this brief allows comparison across different array topologies, process technologies, and circuit choices including assist methods. Using this tool, we find that adding a WL boosting scheme results in an overall energy savings, despite the overhead of using a charge pump circuit, due to an improved read delay distribution.