Abstract

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz.

Highlights

  • Delay-Locked Loops (DLLs) with high-resolution delay steps are extensively used for time management of large systems [1]

  • DLLs are used in the compensation for PVT variations and any delay mismatch that may be caused to signals during the operation of many high-frequency VLSI circuits [3]

  • For all of these applications, DLLs should generate an adequate amount of lock/delay range while maintaining the output jitter as low as possible

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Summary

Introduction

Delay-Locked Loops (DLLs) with high-resolution delay steps are extensively used for time management of large systems [1]. The capacitor-reset technique is widely used to reinitialize a control voltage to a fixed initial value and has been applied in many circuits such as pixels of image sensors and PLL circuits [10,11] At this point, mathematical analysis confirmed by circuit simulation, our proposed technique is capable of generating a comparably wide delay range and picosecond-resolution delay steps with a sub-picosecond jitter performance. Mathematical analysis confirmed by circuit simulation, our proposed technique is capable of generating a comparably wide delay range and picosecond-resolution delay steps with a sub-picosecond jitter performance This architecture consumes a relatively small area and power compared with the available techniques reported in literature.

Materials and Methods
Discussion
Voltage
10. Figure
11. Maximum
13. RMS supply
50 MHz–2 GHz
50 MHz–271
Conclusions

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