Abstract
As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.
Highlights
The need for low-power circuits has drastically increased with the wide spread of mobile applications and wearable devices
To reduce the leakage current, the method of increasing the threshold voltage with an internal negative voltage generator is truly vital for DRAMs [4,7,8]
Generator withand a high and fast pump down speed at very low supply voltage
Summary
The need for low-power circuits has drastically increased with the wide spread of mobile applications and wearable devices. A crosshybrid charge pump circuit (CHPC1) [11] is introduced to improve the pump down speed and coupled hybrid charge pump circuit (CHPC1) [11] is introduced to improve the pump down speed pumping efficiency at low VDD. This circuit has two pumping branches whose controls are provided and pumping efficiency at low VDD This circuit has two pumping branches whose controls are by non-overlapping clock signals. CHPC1 increases the pump down speed using sequential pump provided by non-overlapping clock signals. CHPC1 increases the pump down speed using sequential down operations and mitigates VDD constraints using non-overlapping pumping clocks. Wea present charge pump circuit pumping clock to serveclock as a negative generator with a negative charge using pumpenhanced circuit using enhanced pumping to serve voltage as a negative voltage a high efficiency fastefficiency pump down speed at very low supply voltage.
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
