Charge-based Capacitance Measurement Research Articles

An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

Precision measurement of pixel sensor capacitance

The capacitance of the charge collection node of a sensor system is an important parameter for the design of the analog front-end electronics. The analog front-end of high-granularity sensors like for example hybrid pixel detectors need to be optimized for timing resolution, power consumption, and electronics noise—parameters which all depend on the pixel capacitance. Current pixel detector developments for the HL-LHC upgrade typically use silicon sensors with a pixel size in the order of 50 × 50 μm2 which have a pixel capacitance of several tens of fF, depending on the sensor geometry. We have developed a dedicated integrated circuit to be bump-bonded to a pixel sensor, which enables a precise pixel capacitance measurement by using the charge-based capacitance measurement method. In this paper, we will describe the measurement method and the implementation of the capacitance measurement chip (Pixcap65) and show measurement results of a planar pixel sensor whose pixel capacitance is influenced by variations of the implant geometry.

Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry.

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

Development of air-gap etching process by a mask approach for characterization of intralayer and interlayer capacitances

An air-gap structure was implemented in the metal 2 (M2) layer of a copper interconnect by a mask approach. The fabrication of the air-gap was achieved by tuning etching process parameters such as temperature and etchant chemistry. A residue-free copper surface was realized by optimizing the different steps in the air-gap etching process. The M2 intralayer and interlayer capacitances were measured by using the charge-based capacitance measurement (CBCM) technique and compared with the simulation. Results show that, after the air-gap etching process, with the deposition of 150 Å SiCN on the M2 line with a width of 90 nm, a 22% intralayer capacitance drop was found in the M2 and the 16% ring oscillator frequency was improved. An increase in interlayer capacitance was observed, which resulted from the SiCN thickness decrease on the M2 layer and without the use of dielectric planarization after air-gap formation.

Study on effective MOSFET channel length extracted from gate capacitance

The effective channel length (LGCM) of metal–oxide–semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which LGCM is extracted. It is found that LGCM is slightly less than the effective channel length (LCRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

All Regimes Parasitic Capacitances Extraction Using a Multi-Channel CBCM Technique

In this paper, we propose a multi-channel charge-based capacitance measurement (MCCBCM) technique for parasitic capacitances extraction of MOSFETs. The proposed technique is developed from a leakage- and parasitic-insensitive charge-based capacitance measurement technique, which is applied to measure gate-to-channel capacitance in certain regimes. Using the MCCBCM technique, we can measure all of the parasitic capacitance components of an MOSFET which are related to its terminals, such as the gate-to drain capacitance ( $ {C_{GD}}$ ), gate-to-source capacitance ( $ {C_{GS}}$ ), gate-to-bulk capacitance ( $ {C_{GB}}$ ), and so on. We designed a complex control methodology for the MCCBCM circuit. Specific control methods are provided for different parasitic capacitance components when MOSFETs work in different regimes. We can measure capacitances of sub-femto-farad level in all regimes, including the accumulation, depletion, and inversion regimes.

Monitoring Test Structure for Plasma Process-Induced Charging Damage Using Charge-Based Capacitance Measurements

A novel monitoring test structure is proposed for plasma process-induced charging damage (PID) based on charge-based capacitance measurement (CBCM), referred to as PID–CBCM. By eliminating antenna capacitance interferences, a remarkably smaller gate capacitance (tens of fF) can be obtained for effectively evaluating the influence of PID on metal oxide semiconductor field-effect transistors (MOSFETs). Moreover, the interface trap density can be extracted simultaneously using PID–CBCM implemented with modified charge pumping measurements. Furthermore, another type of PID–CBCM structure under unique measurement conditions has been developed to evaluate drain current (Id) as a function of gate voltage (Vg). The new structure works by extracting the threshold voltage (Vth) shifts on the basis of capacitance–voltage (C–V) characteristics after applying a stress voltage to the gate oxide of devices under test in the PID–CBCM structure. Based on these approaches, three meaningful characteristics of the PID are obtained: 1) Vth shifts extracted from C–V characteristics; 2) Vth shifts extracted from Id–Vg characteristics; and 3) interface trap density extracted from charge-pumping current. Thus, the effects of PID on MOSFET can be monitored over suitably small areas such as scribe-line and chip areas.

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm ? 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.

Study on Threshold Voltage Variation Evaluated by Charge-Based Capacitance Measurement

Study on Threshold Voltage Variation Evaluated by Charge-Based Capacitance Measurement

Gate Capacitance Measurement Using a Self-Differential Charge-Based Capacitance Measurement Method

In this letter, we propose a self-differential charge-based capacitance measurement(SDCBCM) method. It is specifically applied to measure MOSFET gate capacitance with high accuracy. SDCBCM has two main advantages. First, it employs a newly proposed self-differential method to derive the capacitance-voltage ( $C$ – $V$ ) curve of gate capacitance, thus avoiding the amplification of systematic error during the differentiation. Second, it can operate at a very high frequency (500 MHz or more), which for the first time allows the gate capacitance of actual operating frequency to be measured and reduces random error to a very low level. Compared with the previous work, the accuracy of our method is increased by tens of times.

A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit

In this paper, a new on-chip signal generator for charge-based capacitance measurement (CBCM) circuit is proposed. As compared to conventional circuits that use two input off-chip clock signals or on-chip delay cells, the proposed circuit uses an I/Q splitter and an AND function to obtain 1/2 and 1/8 duty cycle signals, hence reduces the potential mismatch between these two clock signals. The proposed circuit makes it possible to use higher input frequency in measurement. As a result, smaller capacitance can be measured using the same measurement facilities without the loss of accuracy. Implemented in a standard 180 nm CMOS process, the proposed signal generator only occupies 40 μm?×?18 μm while consuming less than 60 μW at an input frequency of 100 MHz. Simulation and measurement results suggest that the CBCM measuring circuits with proposed signal generator achieves the same accuracy as compared to conventional circuits while the requirement of measurement facilities can be considerably relaxed.

Extraction of geometry-related interconnect variation based on parasitic capacitance data

A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.

A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents.

Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array

To address the need for direct extraction of the capacitance of a chip, a capacitance measurement array (CMA) has been developed. The operation of the CMA is based on the charge-based capacitance measurement (CBCM) technique. The CMA chip consists of 144 CBCM array units (CAU) and each CAU is designed to measure eight individual capacitors. Element selection and precise measurement are achieved using three-stage transmission gates with four address lines, to ensure a measurement accuracy for capacitor of 1 fF. Different components of the capacitance measurement are addressed and the parameters of CAU are varied to determine the individual influence of these factors. Different physical capacitor shapes are examined to show the capacitance variation as a result of changes to the horizontal and vertical dimensions. MOS transistors with different channel widths are used to illustrate the driving capability influence. The chip is fabricated by a 180 nm CMOS process with six metallic interconnect layers. Based on the results of capacitance array measurement, the capacitance variation in the chip can also be determined. The full address capacitance is measured and the sample data are decomposed into systematic and random variation components using a third-order polynomial fitting for the chip.

Fast and Accurate Characterization of MOS and Interconnect Capacitance Using Direct Charge Measurement (DCM)

A fast and accurate capacitance measurement technique, direct charge measurement (DCM), is introduced to improve productivity of semiconductor parametric testing. The approach is simpler and much faster compared with conventional method using charge-based capacitance measurement (CBCM) or LCR meter. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. The basic theory, parallel measurement method and mathematical analysis on non-linear MOS capacitance measurement are explained. For interconnect capacitance measurement, an extension of DCM, degenerated exhaustive direct charge measurement (DEDCM) is presented as a faster, more accurate and thorough characterization technique. Experimental results show good data matching and significant throughput improvement over conventional LCR meter measurements.

On-Chip Combined C-V/I-V Characterization System in 45-nm CMOS Technology

An on-chip system for combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the underlying physical characteristics of the device, including line-edge-roughness (LER) parameters and systematic device length variations across the die.

Influence of Geometry on the Memristive Behavior of the Domain Wall Spintronic Memristors and Its Applications for Measurement

A memristor is characterized by its electrical memory resistance (memristance), which is a function of the historic profile of the applied current (voltage). This unique ability allows reducing charge- and flux-based measurements to straightforward resistance measurements. The memristive measurement seeks a memristor with a constant modulation of the memristance (memductance) with respect to the charge (flux) for charge (flux)-based measurements. In this work the geometry dependent memristive behavior of a spintronic device is studied to demonstrate the possibility of both charge- and flux-based sensing, using spintronic memristors with different device geometries. The dynamic properties of a propagating magnetic domain wall in different geometrical structures make the spintronic memristor suitable for the charge-based capacitance and flux-based inductance measurements.

Wireless Charge Based Capacitance Measurement Circuits with On-Chip Spiral Inductor for Radio Frequency Identification Biosensor

A wireless measuring system of charge based capacitance measurement (CBCM) circuit has been designed and demonstrated for biomedical applications. The radio frequency identification (RFID) chip that includes on-chip spiral inductor tag antenna, and RFID circuit, and CBCM sensor chip are fabricated within standard complementary metal oxide semiconductor (CMOS) process. The capacitance change caused by DNA detection can be converted into the voltage output using capacitance-to-voltage conversion circuit. To confirm the transmission of the capacitance, the poly-capacitor of fixed capacitance and on-chip spiral inductor tag antenna were fabricated using 1.2 µm, 2-metal, 2-poly CMOS technology. As a result of measurement, three different capacitances (34, 141, 564 fF) were detected wirelessly.

Wireless Charge Based Capacitance Measurement Circuits with On-Chip Spiral Inductor for Radio Frequency Identification Biosensor

A wireless measuring system of charge based capacitance measurement (CBCM) circuit has been designed and demonstrated for biomedical applications. The radio frequency identification (RFID) chip that includes on-chip spiral inductor tag antenna, and RFID circuit, and CBCM sensor chip are fabricated within standard complementary metal oxide semiconductor (CMOS) process. The capacitance change caused by DNA detection can be converted into the voltage output using capacitance-to-voltage conversion circuit. To confirm the transmission of the capacitance, the poly-capacitor of fixed capacitance and on-chip spiral inductor tag antenna were fabricated using 1.2 µm, 2-metal, 2-poly CMOS technology. As a result of measurement, three different capacitances (34, 141, 564 fF) were detected wirelessly.

On-chip Microelectrode Capacitance Measurement for Biosensing Applications

Charge-based capacitance measurement (CBCM) is used to implement an on-chip microelectrode biosensor combined with complementary metal oxide semiconductor (CMOS) circuitry. Electrical double-layer capacitance is exploited to measure the interfacial property changes during biorecognition events at electrode surfaces. A test chip with 4 ×4 µm2 planar electrodes and a differential capacitance-to-voltage conversion circuit was designed and fabricated using 1.2 µm CMOS technology. The chip was experimentally characterized in sodium chloride (NaCl) aqueous solutions to demonstrate its feasibility to detect capacitance variation when the ionic concentration is varied between 0.1 mM and 1 M over a wide frequency range. To show the feasibility of the microfabricated electrode for detecting biomaterials in such a small sensor area, the hybridization of 20-mer probe oligonucleotides in a phosphate-buffered solution was demonstrated. A 20% change in capacitance (10 fF) before and after the injection of complimentary target oligonucleotides is successfully observed, showing promise for future miniature yet high-throughput biosensor arrays.